Thanks to visit codestin.com
Credit goes to github.com

Skip to content
View jordancarlin's full-sized avatar

Highlights

  • Pro

Organizations

@openhwgroup

Block or report jordancarlin

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

The purpose of the repo is to support CORE-V Wally architectural verification

SystemVerilog 14 39 Updated Oct 13, 2025

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

SystemVerilog 1 Updated Oct 22, 2025

RISC-V Instruction Set Manual

TeX 4,318 755 Updated Oct 20, 2025

Sail RISC-V model

Sail 616 232 Updated Oct 21, 2025

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

SystemVerilog 430 315 Updated Oct 22, 2025