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1. OpenLane_Workshop OpenLane_Workshop Public

   In this repository I have pushed my work, which was updated throughout the workshop on OpenLane and other Open source tools based work on Digital VLSI SoC Design

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2. Advanced-Lane-Lines Advanced-Lane-Lines Public

   Forked from Dt-Pham/Advanced-Lane-Lines

   A pipeline that can detects lane boundaries, predicts upcoming curves, and measures lane curvature.

   Jupyter Notebook

3. Verilog-Codes-HDLBits Verilog-Codes-HDLBits Public

4. CompressorBasedMultiplier CompressorBasedMultiplier Public

   In this repo, I have designed a 4-2 compressor and 3-2 compressor based 8x8 dadda multiplier

   Verilog

5. RISC-V-Workshop RISC-V-Workshop Public

   In here, I have uploaded my work on the developement of the RISC-V microarchitecture, constructed using TL-Verilog in the Makerchip IDE, as part of VSD and NASSCOM certified 'RISC-V based MYTH' pro…

   TL-Verilog

6. Traffic-Signal-Controller Traffic-Signal-Controller Public

   A simple Logic Synthesis project where I have designed and simulated a traffic signal controller, which regulates traffic signals along NS and EW directions. The top module, the related modules and…

   Verilog