Super ATX Power!

16 Synchronized Inputs USB (UAC2) Sound Card Based on XMOS xCORE-200

Button driver for embedded system

VSCode extension for enhancing verilog

mor1kx - an OpenRISC 1000 processor IP core

HDL libraries and projects

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter

A cross-platform command-line utility that creates projects from cookiecutters (project templates), e.g. Python package projects, C projects.

电子科技大学毕设设计论文LaTeX模板

A demo implementation of a clean architecture in Python

Files in this folder is a public one, used for learning Python.

Xilinx Tcl Store

Repo for counting stars and contributing. Press F to pay respect to glorious developers.

Chisel: A Modern Hardware Design Language