Very simple RISC-V emulator. Reads ELF file and execute in emulator.

Basic usage with an interactive debug console:

emu6 <ELF File> -d

Currently the CPU configuration is generated from ELF files.

Use emu6 --help for further usage instructions.

The target of this project is to support emulating heterogeneous CPUs and several common SoC peripherals in all mainstream host operating systems. For example on heterogeneous SoC, it's expected to support debugging one Cortex-M and one RISC-V core sharing same memory region running at the same time.

Software features:

• Load one ELF file
• Interactive debug shell
• A friendly plugin system
• DTB support
• Support multiple ELF files
• RISC-V ISA support
• Thumb-2 ISA support
• GDB server
• Cache model

RISC-V instruction set and features:

• RV32I
• RV64I
• RV128I
• Extension M
• Extension A
• Extension F
• Extension D
• Extension C
• Extension V
• Zicsr
• Zifencei
• User mode
• Supervisor mode
• Sv32
• Sv39
• Sv48
• PLIC
• CLINT

This project is written in Rust. You need to [have Rust toolchain installed] before all the processes.

have Rust toolchain installed

git clone https://github.com/luojia65/emu6
cd emu6
cargo run

If the target feature is defined in the ISA's official manual, write into project itself. If it's vendor defined, write as plugins.