Utility features for Yjs

A music theory library for Javascript

Searching Open Library by keywords to return ISBNs

String validation

Simple JavaScript chess engine without dependencies written in NodeJs. It can be used on both, server or client (web browser) and do not need persistent storage - handy for serverless solutions lik…

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Random instruction generator for RISC-V processor verification

RISC-V Instruction Set Manual

The official Semantic-UI-React integration

Source files for SiFive's Freedom platforms

Universal utility for programming FPGA

Semantic is a UI component framework based around useful principles from natural language.

Take control of your Colorlight FPGA board with LiteX/LiteEth :)

Defund the Police.

wolfBoot is a portable, OS-agnostic, secure bootloader for microcontrollers, supporting firmware authentication and firmware update mechanisms.

A mini-preprocessor library to demostrate the recursive capabilites of the preprocessor

A FPGA friendly 32 bit RISC-V CPU implementation

Rocket Chip Generator

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems

OpenThread released by Google is an open-source implementation of the Thread networking protocol

CBOR library aimed at heavily constrained devices

Principles to help you design and deploy a zero trust architecture

Initialization code ("crt0") written in Rust

Minimal runtime / startup for RISC-V CPU's.

Low level access to RISC-V processors

Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

p0f unofficial git repo