[ExportVerilog] Add a lowering option to fix up empty modules #7454
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This commit adds a new lowering option to sanitize empty modules by creating a dummy wire in it.
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prithayan
approved these changes
Aug 7, 2024
fabianschuiki
approved these changes
Aug 8, 2024
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This commit adds a new lowering option to sanitize empty modules by creating a dummy wire in it.