[VerifToSMT] Fix incorrect loop region result indexing #8006
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maerhart
approved these changes
Jan 7, 2025
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Fixes a bug introduced in #7878 where the wrong index is used to access the results of the loop region, often leading to a crash when the clock isn't the first input to the original module. Also includes a breaking example as a test - I've added it in a new file to avoid the different BMC circuit/loop/init functions from this and the other BMC test interleaving, can merge it into the existing test file if preferred and just interleave the Filecheck commands.