This commit implements lowering for shift operations. They are currently lowered into mux-trees with a gate condition for out-of-bounds, e.g.:

```mlir
hw.module @Shift3(in %lhs: i3, in %rhs: i3, out out_shl: i3, out out_shr: i3, out out_shrs: i3) {
  %0 = comb.shl %lhs, %rhs : i3
  %1 = comb.shru %lhs, %rhs : i3
  %2 = comb.shrs %lhs, %rhs : i3
  hw.output %0, %1, %2 : i3, i3, i3
}
```

```verilog
$ circt-opt --pass-pipeline="builtin.module(hw.module(convert-comb-to-aig{additional-legal-ops=comb.xor,comb.or,comb.and,comb.mux,comb.add,comb.icmp},convert-aig-to-comb),export-verilog)" bar.mlir

module shift3(  // bar.mlir:2:1
  input  [2:0] lhs,     // bar.mlir:2:22
               rhs,     // bar.mlir:2:35
  output [2:0] out_shl, // bar.mlir:2:49
               out_shr, // bar.mlir:2:66
               out_shrs // bar.mlir:2:83
);

  wire [2:0] _GEN = {3{lhs[2]}};        // bar.mlir:5:8
  assign out_shl =
    rhs < 3'h3
      ? (rhs[1] ? (rhs[0] ? 3'h0 : {lhs[0], 2'h0}) : rhs[0] ? {lhs[1:0], 1'h0} : lhs)
      : 3'h0;   // bar.mlir:2:35, :3:8, :6:3
  assign out_shr =
    rhs < 3'h3
      ? (rhs[1] ? (rhs[0] ? 3'h0 : {2'h0, lhs[2]}) : rhs[0] ? {1'h0, lhs[2:1]} : lhs)
      : 3'h0;   // bar.mlir:2:35, :4:8, :6:3
  assign out_shrs =
    rhs < 3'h3
      ? (rhs[1]
           ? (rhs[0] ? _GEN : {3{lhs[2]}})
           : rhs[0] ? {{2{lhs[2]}}, lhs[1]} : {lhs[2], lhs[1:0]})
      : _GEN;   // bar.mlir:2:35, :5:8, :6:3
endmodule

```