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[ExportVerilog] localparam should always print bitwidths #8732

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Merged
merged 1 commit into from
Jul 18, 2025
Merged

[ExportVerilog] localparam should always print bitwidths #8732

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8 changes: 7 additions & 1 deletion lib/Conversion/ExportVerilog/ExportVerilog.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5907,6 +5907,11 @@ LogicalResult StmtEmitter::emitDeclaration(Operation *op) {
auto type = value.getType();
auto word = getVerilogDeclWord(op, emitter);
auto isZeroBit = isZeroBitType(type);

// LocalParams always need the bitwidth, otherwise they are considered to have
// an unknown size.
bool singleBitDefaultType = !isa<LocalParamOp>(op);

ps.scopedBox(isZeroBit ? PP::neverbox : PP::ibox2, [&]() {
unsigned targetColumn = 0;
unsigned column = 0;
Expand All @@ -5930,7 +5935,8 @@ LogicalResult StmtEmitter::emitDeclaration(Operation *op) {
{
llvm::raw_svector_ostream stringStream(typeString);
emitter.printPackedType(stripUnpackedTypes(type), stringStream,
op->getLoc());
op->getLoc(), /*optionalAliasType=*/{},
/*implicitIntType=*/true, singleBitDefaultType);
}
// Emit the type.
if (maxTypeWidth > 0)
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2 changes: 1 addition & 1 deletion test/Conversion/ExportVerilog/name-legalize.mlir
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Expand Up @@ -57,7 +57,7 @@ hw.module @parametersNameConflict<p2: i42 = 17, wire: i1>(in %p1: i8) {

// CHECK: `ifdef SOMEMACRO
sv.ifdef @SOMEMACRO {
// CHECK: localparam local_0 = wire_0;
// CHECK: localparam [0:0] local_0 = wire_0;
%local = sv.localparam { value = #hw.param.decl.ref<"wire">: i1 } : i1

// CHECK: assign myWire = wire_0;
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