[circt-verilog] Add register-to-memory pass to pipeline #8773
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Add the new RegOfVecToMem pass to the circt-verilog pipeline. This will detect memories described as `always` blocks and map them from the current `seq.firreg` representation to the correpsonding `seq.firmem`. This allows later parts of the pipeline to reason about memories more easily and transform them if needed.
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Add the new RegOfVecToMem pass to the circt-verilog pipeline. This will detect memories described as
alwaysblocks and map them from the currentseq.firregrepresentation to the correpsondingseq.firmem. This allows later parts of the pipeline to reason about memories more easily and transform them if needed.