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@SimonEbner SimonEbner commented Oct 9, 2025

Added a testcase that is the result of parsing the following sv code:

module bug (
  input logic [1:0][1:0][1:0] in,
  output logic [1:0] out
);
assign out = in[0][0][1:0];

endmodule

The current MooreToCore pass translates the sv ode incorrectly to

hw.module @bug(in %in : !hw.array<2xarray<2xi2>>, out out : i2) {
  %false = hw.constant false
  %0 = builtin.unrealized_conversion_cast %in : !hw.array<2xarray<2xi2>> to !hw.array<2xi2>
  %1 = hw.array_get %0[%false] : !hw.array<2xi2>, i1
  hw.output %1 : i2
}

Adding a check if operand and result array have the same level of nesting in the ExtractOpConversion fixes the bug.

@SimonEbner SimonEbner changed the title Support slicing of nested arrays. [MooreToCore] Support slicing of nested arrays. Oct 9, 2025
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@fabianschuiki fabianschuiki left a comment

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Thanks a lot for finding and fixing this!

Comment on lines 734 to 747
if (auto resArrTy = dyn_cast<hw::ArrayType>(resultType)) {
if (auto resArrTy = dyn_cast<hw::ArrayType>(resultType);
resArrTy && arrayNestingLevel(resArrTy) == arrayNestingLevel(arrTy)) {
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I remember @jpienaar fixing a similar issue for ExtractRefOp a few weeks ago:

https://github.com/llvm/circt/pull/8942/files#diff-69352128fb82df4324ed3a5ea9e15dda3bd643c2c183d66e8e1bcd15d01246f9R838-R841

Do you think we could use a similar way of checking for slicing vs. element access, by checking whether the arrType.getElementType() != resultType? That would avoid having to reason about nesting levels of arrays, and would turn this into a quick pointer equality check.

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That seems way better. I updated the code. Initially, I wasn't sure if there may be edge-cases I hadn't thought about. All tests pass though.

@fabianschuiki fabianschuiki added Moore bug Something isn't working labels Oct 9, 2025
@SimonEbner SimonEbner force-pushed the unrealized_conversion branch 2 times, most recently from 9261708 to a4de7d6 Compare October 10, 2025 06:57
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Really neat! πŸ₯³ Thanks a lot. Will land this as soon as CI has run through.

Added a testcase that is the result of parsing the following sv code:

```sv
module bug (
  input logic [1:0][1:0][1:0] wr_addr,
  output logic [1:0] out
);
assign out = wr_addr[0][0][1:0];

endmodule
```

The current MooreToCore pass translates the sv ode incorrectly to
```
hw.module @bug(in %wr_addr : !hw.array<2xarray<2xi2>>, out out : i2) {
  %false = hw.constant false
  %0 = builtin.unrealized_conversion_cast %wr_addr : !hw.array<2xarray<2xi2>> to !hw.array<2xi2>
  %1 = hw.array_get %0[%false] : !hw.array<2xi2>, i1
  hw.output %1 : i2
}
```

Adding a check if operand and result array have the same level of nesting
in the ExtractOpConversion fixes the bug.
@SimonEbner SimonEbner force-pushed the unrealized_conversion branch from a4de7d6 to c5da9e1 Compare October 10, 2025 17:40
@SimonEbner
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Thanks! I rebased to head to resolve the conflict and pushed my branch again

@fabianschuiki fabianschuiki changed the title [MooreToCore] Support slicing of nested arrays. [MooreToCore] Support slicing of nested arrays Oct 10, 2025
@fabianschuiki fabianschuiki merged commit 7e0b57e into llvm:main Oct 10, 2025
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2 participants