Like VexRiscv, but, Harder, Better, Faster, Stronger

Chisel wrapper for the SpinalHDL VexiiRiscv CPU implementation, implementing Chipyard compatibility

2024最新免费社工库排行

Low Density Parity Check Decoder

Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP

AX7020 board is widely used in security monitoring, automotive electronics, machine vision, intelligent manufacturing, video and audio acquisition and processing, medical equipment, instrumentation…

DQPSK Modem designed by Verilog HDL

eNVMe

1、FPGA Functions as a Transparent Channel to Host

为w25qXX设计的文件系统，支持w25q32、w25q64、w25q128等

🥢像老乡鸡🐔那样做饭。主要部分于2024年完工，非老乡鸡官方仓库。文字来自《老乡鸡菜品溯源报告》，并做归纳、编辑与整理。CookLikeHOC.

Android real-time display control software

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

transplant several overlays to s9_pynq board

Schematics and sample projects for S9 antminer control board sold as development board

Antminer S9 ZYNQ 7010 with PYNQ 2.5 FPGA Dev Board

USB to JTAG / SPI / IIC / GPIO application using ch347 of WCH

Chinese Guide for Alveo Getting Started

Alveo U25 Debug Connector to Xilinx JTAG and UART and I2C Adapter

Setup and Usage Notes for the Zynq XCZU19EG FPGA on the Alveo U25

Build your hardware, easily!

代码在这个库里 Code is here

Compact open-source SDR board with Artix-7, PCIe, GPS, MEMS, and DDR3 — by Novexum™

HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.