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@ksco ksco commented May 16, 2023

Closes #789

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ptitSeb commented May 16, 2023

It broke one test on riscv it seems

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ksco commented May 16, 2023

Hmm, I got a bit confused about this, looks right this time.


#elif defined(__loongarch64) || defined(__powerpc64__) || defined(__riscv)
#undef X64_VA_MAX_XMM
#define X64_VA_MAX_XMM ((6*8)+(8*8))
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Mmm, no, you shouldn't change this variable just for some arch, as it's an x86 one, so it should be common for every arch

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The reg_save_area seems always 8 bytes wide, no matter what type.

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The reg_save_area seems always 8 bytes wide, no matter what type.

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ptitSeb commented May 16, 2023

I'm pretty sure (6 * 8 + 8 * 16) is the right value

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ptitSeb commented May 16, 2023

I think your 1st attempt was correct, with just 1 mystake: you should keep area[fprs/8]because area is a uintptr_t array, and so elements are 8-bytes in size, not 16 bytes (we don't take the whole XMM regs, just a double)

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ksco commented May 16, 2023

Oh yes, that's right. I got confused on the area and fp_offset, they're inconsistent in this situation.

@ptitSeb ptitSeb merged commit d61f3e7 into ptitSeb:main May 16, 2023
@ksco ksco deleted the fix branch May 16, 2023 14:55
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Running VS Code on RISC-V SBC

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