why did you change that? mask 0xE0 or 0xFF LSR 5 give the same result (0x7à

I understand, the original code is work, but it looks strange. I thought 0xE0 is equal to trunc(0xff << 5).

ANDw_mask(s3, s1, 0b011011, 0b000010) execute LSL not LSR, I got a mistake

ANDw_mask just do an AND wisth a constant, there is no LSR/LSL associated

ANDw_mask just do an AND wisth a constant, there is no LSR/LSL associated

I got it, the field immr means rotate.
https://gist.github.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a is helpful, I really shouldn't have ignored it.

Yep. Logic Imm computation is not trivial on arm64. I have some plan to write a function to decompose value if possile, bu it's not done yet.

In here, emit_pf was not used and PF was computed inline to avoid the use of another register. Are you sure it was wrong before?

I guess adding ANDw_REG(s3, s3, s2); after line 299 should fix the computation without the need of the additionnal register.

yes, it was wrong. For example:
int64_t test_32(int r) {
int64_t flags = 0;
asm (
"mov %[_r], %%eax\n"
"test $0x74, %%eax\n"
"mov $0, %%rax\n"
"lahf\n"
"mov %%rax, %[flags]\n"
: [flags] "=m"(flags)
: [_r] "r"(r)
);
return flags;
}

int main() {
assert(0x600 == test_32(0x68));
return 0;
}

I guess adding ANDw_REG(s3, s3, s2); after line 299 should fix the computation without the need of the additionnal register.

Yes, if we caculate the res again, but i think add one sratch register is more clear same as emit_test16 or emit_test8