Verilog implementation of a basic ARM processor with a 5-stage pipeline using only 7 instructions.

To run this, icarus verilog is needed. A simulation build can be assembled by running iverilog -o [OUTPUT FILE] *.v and simulated through vvp [OUTPUT FILE]. By defult, it outputs a waveform of every single wire as dump.vcd

This implementation only contains the following LEGv8 instructions:

The ROM file is a verilog file ROM.v where the main program can be defined. The default program loads a predefined value from DATA_MEM[0] and DATA_MEM[1] and stores it into a register where it is added. Data hazards have not been added yet so it performs some ALU operations in the meantime while the data gets safely stored into the register.