Weekly scheduled pre-release for commit c4d3140.

What's Changed

• Log Sail exceptions into the execution trace. by @pmundkur in #1555

Full Changelog: 0.10...2026-02-23-c4d3140

The highlight of this release is the switch to using the C++ backend of the Sail compiler. The generated model for the hart is wrapped in a C++ class, which opens up the possibility of instantiating multiple harts to simulate multicore platforms (though this is not yet implemented).

A --config-override option has been added to specify one or more additional JSON configuration files that override the corresponding fields in a configuration.

This release adds 9 extensions and 2 unratified extensions. The unratified extensions require the --enable-experimental-extensions option to be activated.

More details, including updates to the configuration file and important bug fixes, are in the release notes.

Weekly scheduled pre-release for commit a33475a.

What's Changed

• Strengthen some before statements in sail_project file by @Alasdair in #1537
• Install newer Clang version on Linux CI for newer extension support by @nadime15 in #1532
• Make global g_model instance local by @Timmmm in #1536
• Improve README. by @pmundkur in #1540
• Fix fcvt.s.bf16 NaN-boxing returning wrong canonical QNaN by @nadime15 in #1528
• Add --config-override flag for configuration overrides by @trdthg in #1534
• Add missed stateen checks for the high-half CSRs of hstateen[0-3]. by @pmundkur in #1546
• Add the Rocky Linux container build to CI. by @pmundkur in #1542
• Use FetchContent for CLI11 and bump to v2.6.1 by @trdthg in #1544
• Adapt the release workflow to use the common sail-setup action. by @pmundkur in #1543
• Update changelog for version 0.10. by @pmundkur in #1526
• Update version. by @pmundkur in #1552

Full Changelog: 2026-02-09-de7c9e8...2026-02-16-a33475a

Weekly scheduled pre-release for commit de7c9e8.

What's Changed

• Fix typo in directory and module name: Zifenci -> Zifencei. by @pmundkur in #1519
• Declare reservation callbacks for C for use in Isla. by @pmundkur in #1516
• Fix CSR privilege check for hypervisor mode. by @pmundkur in #1504
• Update test suite. by @pmundkur in #1523
• Add LCOFI interrupt missed in Sscofpmf. by @pmundkur in #1520
• Use C++ chrono for benchmarking instead of gettimeofday by @Timmmm in #1498
• Add unratified Zvabd extension by @TinyuengKwan in #1478
• Validate vector register groups. by @pmundkur in #1486
• Add info on contributing extensions under development. by @pmundkur in #1521
• Remove config_enable_rvfi checks from RVFI callbacks by @Timmmm in #1525
• Remove unncessary void parameters in riscv_sim.cpp by @Timmmm in #1530
• Move CLI options into struct by @Timmmm in #1529
• Return instead of exit() in inner_main() by @Timmmm in #1531
• Make config settings non-global by @Timmmm in #1535
• Remove some unused string mappings. by @pmundkur in #1538

New Contributors

• @TinyuengKwan made their first contribution in #1478

Full Changelog: 2026-02-02-e7e6e07...2026-02-09-de7c9e8

Weekly scheduled pre-release for commit e7e6e07.

What's Changed

• Add a missed file for the Lean build fix in #1499. by @pmundkur in #1505
• Ensure physical memory access checks are not bypassed for failing store-conditionals. by @pmundkur in #1500
• Fix the first party linker map to be more consistent with the default config. by @pmundkur in #1512
• Print registers in AMOCAS reserved message by @challenger1024 in #1510
• Add configuration option to handle reserved dynamic rounding modes. by @challenger1024 in #1491
• Add the Zibi extension. by @challenger1024 in #1507

Full Changelog: 2026-01-26-89935a8...2026-02-02-e7e6e07

Weekly scheduled pre-release for commit 89935a8.

What's Changed

• Update OpenSBI to v1.8.1 by @jordancarlin in #1477
• Add support for Smstateen and Ssstateen extensions by @nadime15 in #910
• Rename the ext_access_type type to mem_payload. by @pmundkur in #1479
• Add configuration option for reserved behavior xenvcfg.CBIE = 0b10 by @challenger1024 in #1447
• Add Hypervisor interrupt causes by @nadime15 in #1481
• Get semicolon-separated list of source files from Sail by @Timmmm in #1484
• Use bits(1) and 0b0/0b1 consistently in place of bit and bitone/bitzero by @jordancarlin in #1483
• Add Hypervisor exception causes by @nadime15 in #1480
• Whitespace and alignment fixes for vector files. by @pmundkur in #1487
• Use builtin CMake variables to identify compiler by @Timmmm in #1488
• Add hypervisor helper to check if privilege level is virtual mode by @nadime15 in #1482
• Add Ssqosid extension by @ved-rivos in #379
• Refactor the memory access type. by @pmundkur in #1405
• Fix model compilation by @Timmmm in #1494
• Remove N extension InterruptType values by @KotorinMinami in #1492
• Add rocq sys_enable_experimental_extensions definition by @jordancarlin in #1497
• Update Lean builds to use separate Sail support library by @bacam in #1499
• Fix a couple of TODOs now that the VU mode and virtual instruction exceptions are defined. by @pmundkur in #1501
• Add configuration option for reserved behavior: odd number register for RV32Zdinx by @challenger1024 in #1462

Full Changelog: 2026-01-12-397a7e8...2026-01-26-89935a8

Weekly scheduled pre-release for commit 397a7e8.

What's Changed

• Improve float classify code by @Timmmm in #1288
• Use let instead of register for plat_clint config variables by @jordancarlin in #1349
• Simplify vector_support_level by @KotorinMinami in #1348
• Add Zic64b extension by @jordancarlin in #1351
• Add gating for vector instructions. by @wwwwwwOwO in #1170
• Bump actions/upload-artifact from 4 to 5 by @dependabot[bot] in #1360
• Bump actions/download-artifact from 5 to 6 by @dependabot[bot] in #1361
• Rocq updates by @bacam in #1359
• Add more state change callbacks by @Timmmm in #1354
• Add an option to choose a smaller set of modules for Lean build by @Alasdair in #1219
• Unify the handling logic for scalar and vector multiplication. by @KotorinMinami in #1299
• Refactor immediates in encoding clauses for readability. by @pmundkur in #1364
• Always validate JSON config by @Arielfoever in #1296
• Add new sail_smt_cache to git ignore list by @Arielfoever in #1373
• Bump jsoncons to version 1.4.3 by @Arielfoever in #1371
• Rename build_simulators.sh since there is only one simulator now. by @pmundkur in #1379
• Allow configuring read-only-zero PMP entries. by @pmundkur in #1363
• Document how to add an experimental extension. by @pmundkur in #1378
• Rename the AccessType for memory to be more explicit. by @pmundkur in #1368
• Innocuous typo in constructor name by @bacam in #1381
• Implement a more accurate access type for CSR accesses. by @pmundkur in #1369
• Add Sstvecd to supported extensions. by @pmundkur in #1377
• Provide default callback implementations by @Arielfoever in #1372
• Add ExecuteAs result for compressed instructions. by @pmundkur in #1382
• Put Sail smt cache in /build directory by @KotorinMinami in #1384
• Fix htif memory range check by @trdthg in #1380
• Add option not to download jsoncons by @bacam in #1385
• Support a configurable reservation set size. by @pmundkur in #1386
• Add profile-defined extension Ssu64xl. by @pmundkur in #1387
• Add configurations for page-fault traps that could set mtval. by @pmundkur in #1388
• Greatly simplify the code for reading & writing vector registers/masks by @Timmmm in #1213
• Rename some page table walk error results for clarity. by @pmundkur in #1394
• Slight refactor of address translation and PTE checks to ease implementing Zicfiss. by @pmundkur in #1393
• Update clang-format pre-commit hook by @Timmmm in #1398
• Split config_print_platform into finer grained options by @KotorinMinami in #1366
• Fix satp legalization to use Supervisor instead of current privilege by @nadime15 in #1399
• Bump actions/checkout from 5 to 6 by @dependabot[bot] in #1404
• Factor out a prelude module. by @pmundkur in #1406
• Add support for Sstvala. by @pmundkur in #1397
• Make the AMO execute more readable. by @pmundkur in #1407
• Fix unused variable warnings. by @pmundkur in #1409
• Expose per-step pre_step/post_step callbacks by @ibvqeibob in #1395
• Consolidate the indexed vector load and store instructions. by @pmundkur in #1410
• Use C++ Sail output by @Timmmm in #1274
• Simplify read/write kinds by @Timmmm in #1262
• Scatter termination.sail by @Ptival in #1376
• Add callbacks and logging for page table walks by @Arielfoever in #1370
• Lean: adapt to Sail change by @ineol in #1420
• add ConcurrencyInterfaceV1 as required by Nov lean nightly toolchain by @jn80842 in #1423
• Bump actions/upload-artifact from 5 to 6 by @dependabot[bot] in #1425
• Bump actions/cache from 4 to 5 by @dependabot[bot] in #1427
• Bump actions/download-artifact from 6 to 7 by @dependabot[bot] in #1426
• Update the build comment that appears in the model build log. by @pmundkur in #1428
• Fix location of the hartSupports_measure function. by @pmundkur in #1429
• Replace hardcoded constant in tlb_hash() with a compile-time constant by @nadime15 in #1421
• Add Zdinx to configuration and validate Zfinx-related dependencies by @nadime15 in #1431
• Update pre-commit config. by @pmundkur in #1433
• Ensure that rd is written by vset{i}vl{i} even for illegal and reserved vsew and vlmul. by @pmundkur in #1435
• Rename ext_write_vcsr to just write_vcsr by @pmundkur in #1438
• Improve handling of reserved fences by @Timmmm in #1439
• Add WlfWriteFn type alias to elf_loader.h by @Timmmm in #1448
• Use private keyword in virtual memory code by @Alasdair in #1310
• Add missing csr_write_callback in accrue_fflags by @jordancarlin in #1432
• Improved clang-format style by @Timmmm in #1396
• Fix builds of tests on some platforms. by @pmundkur in #1444
• Bump os-boot Linux and GCC versions by @jordancarlin in #1450
• c_emulator: validate DTB range against configured PMA regions by @ibvqeibob in #1437
• Fix clang-format pre-commit error from #1437 by @jordancarlin in #1454
• Fix compiler warnings on macOS and enable more warnings. by @pmundkur in #1443
• Add reserved_behavior.amocas_odd_registers config by @challenger1024 in #1403
• Bump minimum Sail version to 0.20.1 by @jordancarlin in #1453
• Last remaining refactoring of immediates in encoding clauses for readability. by @pmundkur in #1375
• Flush stdout in flush_logs function by @jordancarlin in #1466
• Update documentation and code style guidelines. by @pmundkur in #1463
• Create weekly binary release by @jordancarlin in #1467
• Remove obsolete TODO from pre-commit config by @jordancarlin in #1473
• Require disclosure of the use of AI tools when contributing. by @pmundkur in #1472
• Add comment to weekly build release schedule by @jordancarlin in #1471
• Use a consistent name for variables of MemoryAccessType. by @pmundkur in #1474
• Add configuration option for reserved behavior pmpcfg with r=0, w=1 by @challenger1024 in #1422
• Centralize memory-access-to-fault conversions. by @pmundkur in #1475

New Contributors

• @ibvqeibob made their first contribution in #1395
• @Ptival made their first contribution in #1376
• @jn80842 made their first contribution in #1423
• @challenger1024 made their first contribution in #1403

Full Changelog: 0.9...2026-01-12-397a7e8

The main features of this release are:

• Support for the RV32E and RV64E ISAs.
• Many more extensions are now supported, for e.g. those for BFloat16.
• Support for Physical Memory Attributes (PMA).
• Validation of the configuration against the configuration schema.
• An ARM binary release for the emulator.
• Updated documentation.

More details are available in the Changelog.

Attestations for the release can be found at https://github.com/riscv/sail-riscv/attestations

This is a major release with some backwards-incompatible changes.

The highlights of the release are:

• A single executable binary for the various ISA versions (RV32/RV64) and floating-point extensions (F/D).

• The introduction of a JSON-based configuration system.

• The use of the Sail module system to provide a modular structure to the RISC-V model.

• Many new extensions, including complete coverage of the RVA23 vector crypto extensions.

• The removal of obsolete in-tree ELF tests in favor of more recent upstream tests (currently from riscv-software-src/riscv-tests and chipsalliance/riscv-vector-tests) in a unified test repo; these upstream tests are now used in CI.

• The removal of obsolete in-tree images for OS boot in favor of build scripts for more recent Linux boot images.

More details are available in the Changelog.

This is the first binary release of the emulators, currently for Linux x86_64 only. These are statically compiled on Rocky 8 with only glibc 2.17 (from 2012) as a dependency so they should run on most distros.

The tarball includes emulators for RV32D and RV64D. If you need RV32F or RV64F you must still compile from source.

The JSON file is intended for use with asciidoctor-sail to allow inclusion of Sail code snippets in documentation.