What's Changed

• [rtl] rework DM by @stnolting in #1396
• 🐛 [rtl] fix CLZ and CTZ instructions by @stnolting in #1397
• [docs] xbus: fix/clarify CTI values by @stnolting in #1399
• [sdext] fix trigger type identification by @stnolting in #1400
• ⚠️ [CFU] remove r4-type instruction support by @stnolting in #1402
• [bus] clean-up processor-internal bus; refine reservation-set controller by @stnolting in #1407
• [sw/example] mark output as early-clobber in unaligned-load test by @vogma in #1406
• [pmp] improve timing by @stnolting in #1408
• counter optimizations and PMP logic cleanup by @stnolting in #1410
• 🐛 [clint] fix register read-back by @stnolting in #1411
• [docs] use Doxygen only for documenting the API by @stnolting in #1413
• Bump actions/download-artifact from 5 to 6 by @dependabot[bot] in #1414
• Bump actions/upload-artifact from 4 to 5 by @dependabot[bot] in #1415
• ✨ [cpu] add experimental support for RISC-V Zibi ISA extension by @stnolting in #1418

Full Changelog: v1.12.3...v1.12.4

This release includes up-to-date PDF builds of the documentation.

• data sheet: NEORV32-nightly.pdf
• user guide: NEORV32_UserGuide-nightly.pdf

What's Changed

• [XBUS] re-add timeout configuration generic by @stnolting in #1383
• Rework execution trace interface by @stnolting in #1384
• 🧪 extend trace port to support "RISC-V formal interface" (RVFI) by @stnolting in #1385
• Rework NEORV32 executable image generator by @stnolting in #1388
• [rtl] minor code cleanups and optimizations by @stnolting in #1389
• rework JTAG interface by @stnolting in #1390
• [rtl] add multiplier primitive by @stnolting in #1391
• 🐛 [rtl] FPU cleanups and minor bug fix by @stnolting in #1392
• 🐛 [dtm] fix bypass register; further code optimizations by @stnolting in #1393
• [system_integration] move libero setup to neorv32-setups repository by @stnolting in #1394
• minor rtl edits and cleanups by @stnolting in #1395

Full Changelog: v1.12.2...v1.12.3

What's Changed

• Rework bootloader; add optional SD card boot option by @stnolting in #1361
• 🐛 [dm] fix command.transfer flag logic by @stnolting in #1363
• minor rtl edits by @stnolting in #1364
• [tracer] update simulation-mode instruction decoding by @stnolting in #1366
• [tracer] update simulation-mode trace logging by @stnolting in #1368
• Bump actions/download-artifact from 4 to 5 by @dependabot[bot] in #1372
• Bump mattnotmitt/doxygen-action from 1.2.1 to 1.12.0 by @dependabot[bot] in #1371
• Bump actions/checkout from 4 to 5 by @dependabot[bot] in #1370
• minor edits and cleanups by @stnolting in #1375
• 🐛 fix unaligned instruction fetch bus error; do not trigger co-processors if instruction exception by @stnolting in #1376
• ⚠️ remove CFU CSRs by @stnolting in #1377
• Correct typo neorv323_package -> neorv32_package by @alyxazon in #1379
• [cpu] minor logic optimizations by @stnolting in #1381

New Contributors

• @dependabot[bot] made their first contribution in #1372
• @alyxazon made their first contribution in #1379

Full Changelog: v1.12.1...v1.12.2

What's Changed

• [rtl] derive all memories from generic RAM primitives by @stnolting in #1347
• [rtl] add all-new FIFO primitive by @stnolting in #1349
• [demo_semihosting] use 4-byte instead of 16-byte alignment by @vogma in #1350
• 🐛 fix simulation memory-component by @stnolting in #1352
• ⚠️ simplify SLINK, SPI and NEOLED modules by @stnolting in #1353
• ⚠️ simplify UART and SDI modules by @stnolting in #1354
• simplify ROM images (VHDL packages for IMEM/BOOTROM) by @stnolting in #1355
• [rtl] minor code-cleanups and optimizations by @stnolting in #1357
• [sdi] add RX & TX FIFO clear flags by @stnolting in #1358
• ⚠️ rework TWD module by @stnolting in #1359
• fix minor RISC-V incompatibilities by @stnolting in #1360

Full Changelog: v1.12.0...v1.12.1

What's Changed

• ⚠️ [CPU] remove double-trap exception by @stnolting in #1332
• minor fixes and optimizations by @stnolting in #1333
• Add NEORV32-specifc "machine control and status" CSR (mxcsr) by @stnolting in #1335
• Add new tuning option: Constant-time branches by @stnolting in #1338
• Rework bus access error logic by @stnolting in #1339
• ⚠️ [SYSINFO] rework layout of "MISC" information register by @stnolting in #1342
• [rtl] replace individual IMEM & DMEM modules by a generic memory component by @stnolting in #1344
• [Vivado IP] Remove relative paths from the IP-packaging script by @stnolting in #1341
• rtl code cleanups and optimizations by @stnolting in #1345
• 🐛 [dma] fix byte-enable signal for byte-reads by @stnolting in #1346

Full Changelog: v1.11.9...v1.12.0

What's Changed

• 🐛 fix double-trap tracking bug by @stnolting in #1312
• ✨ add new module: execution trace buffer (TRACER) by @stnolting in #1313
• Cleanup UART simulation logging by @stnolting in #1314
• Replace trace with trace_s in the top by @Unike267 in #1316
• Add GDB tracer support by @stnolting in #1317
• [tracer] write full trace log to file by @stnolting in #1318
• ✨ add support for RISC-V Zcb ISA extension by @stnolting in #1320
• extend tracer simulation log; improve semihosting by @stnolting in #1322
• Make cache/AXI bursts optional by @stnolting in #1324
• Minor rtl edits and cleanups by @stnolting in #1325
• minor rtl edits and cleanups by @stnolting in #1331

Full Changelog: v1.11.8...v1.11.9

New Features

• add double-trap exception (loosely based on the RISC-V Smdbltrp ISA extension)
• add support for hardware-assisted watchpoints (on-chip debugger)
• add configurable number of hardware break-/watchpoint (0..16)

What's Changed

• remove WDT "strict" bit; minor code edits and cleanups by @stnolting in #1293
• 🧪 add double-trap exception by @stnolting in #1294
• Rework RTE trap handler look-up-table by @stnolting in #1295
• [rte] cleanups and optimizations by @stnolting in #1299
• minor rtl edits and cleanups by @stnolting in #1302
• Feature: Libero support by @hughbreslin in #1300
• [ocd] add support for hardware watchpoints by @stnolting in #1303
• ✨ add configurable number of break-/watchpoints by @stnolting in #1304
• minor rtl edits and cleanups by @stnolting in #1307
• ⚠️ [top] remove HART_BASE generic by @stnolting in #1308
• [cache] fix minimal cache block size by @stnolting in #1310

New Contributors

• @hughbreslin made their first contribution in #1300

Full Changelog: v1.11.7...v1.11.8

What's Changed

• [cpu] Minor rtl optimizations and cleanups by @stnolting in #1283
• upgrade TRNG to neoTRNG v3.3 by @stnolting in #1284
• ✨ on chip debugger: add semihosting support by @stnolting in #1285
• ⚠️ combine SLINK's RX and TX interrupts into a single interrupt by @stnolting in #1286
• ✨ add TRNG interrupt by @stnolting in #1287
• ⚠️ rework UART "TX FIFO full" status flag by @stnolting in #1288
• ⚠️ combine UART's RX and TX interrupts into a single interrupt by @stnolting in #1289
• Minor rtl edits and optimizations by @stnolting in #1291
• Remove enable logic for SoC-wide clock generator by @stnolting in #1292

Full Changelog: v1.11.6...v1.11.7

What's Changed

• 🐛 fix byte-enable bus signal for instruction fetch accesses by @stnolting in #1272
• minor rtl edits and cleanups by @stnolting in #1273
• ⚠️ CFS IO rework by @stnolting in #1274
• ⚠️ remove CRC module by @stnolting in #1275
• Rework IMEM & DMEM RAM style by @stnolting in #1277
• [cpu] rework instruction trap logic by @stnolting in #1278
• 🧪 rework DMA controller by @stnolting in #1279
• ⚠️ Rename IMEM/DMEM configuration generics by @stnolting in #1280
• Add optional IMEM/DMEM output register stages by @stnolting in #1281

Full Changelog: v1.11.5...v1.11.6