This repository showcases various advanced techniques for Retrieval-Augmented Generation (RAG) systems. RAG systems combine information retrieval with generative models to provide accurate and cont…

A minimal GPU design in Verilog to learn how GPUs work from the ground up

I'm sick of complex blogging solutions, so markdown files in a git repo it is

round robin arbiter

Ethernet MAC 10/100 Mbps

1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)

Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

RISC-V XV6/Linux SoC, marchID: 0x2b

Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably …

VRoom! RISC-V CPU

A small, light weight, RISC CPU soft core

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Examples for learning how to write linux device drivers following ldd3

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

Verilog code for a circuit implementation of Radix-2 FFT

LUFA - the Lightweight USB Framework for AVRs.

📖 List of FPGA Lattice boards using open tools

Open source implementation of a x86 processor

Multi-platform nightly builds of open source FPGA tools

A series of CORDIC related projects

Random ideas and interesting ideas for things we hope to eventually do.

Turn WaveDrom timing diagrams into ASCII art

A list of ICs and IPs for AI, Machine Learning and Deep Learning.

Explanation of ncverilog error messages. Nothing fancy; just a text file.

A Gatsby blog theme.

Generate testbench for your verilog module.

Complete flight control system designed from scratch. Hardware designed with KiCad.

Blake's embedded projects

🌊 Digital timing diagram rendering engine