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1. MyCaptain-AI-Course MyCaptain-AI-Course Public

   Course Tasks Done by Surya Lolla

   Jupyter Notebook

2. Parameter-Registry Parameter-Registry Public

   SystemVerilog

3. Pulse-Generator-250nm_TannerEDA Pulse-Generator-250nm_TannerEDA Public

   Forked from NishchalAV/Pulse-Generator-250nm_TannerEDA

   Using a pulse wave as an input referencing as clock we try to generate three different pulses having different pulse width

   SourcePawn

4. Phase-locked-loop_VLSI Phase-locked-loop_VLSI Public

   Frequency synthesizer circuit design

5. FFVDD-PROJECT FFVDD-PROJECT Public

   SystemVerilog

6. Digital-Design-of-AlarmClock Digital-Design-of-AlarmClock Public

   SystemVerilog