Rv32i Five Stage Pipelined Core in CHISEL HDL

• SBT >= 1.9.7
• Verilator >= 5.012
• Chisel >= 7.0.0.

git clone https://github.com/shahzaibk23/core

sbt "runMain core.CoreDriver --imem /path/to/imem --dmem /path/to/dmem --target-dir /out/dir/

All Modules' .sv files will be dumped in the --target-dir directory.

• Add you instructions' hex in instrx.hex
• Run the Command

sbt "testOnly core.Top_test -- -DemitVcd=1"

• This will dump the .vcd in path build/chiselsim/Top_test/Top-under-test/workdir-verilator/trace.vcd

• Update the paths to your imem and dmem in src/test/scala/core/TopTracer_test.scala
• Run the command

sbt "testOnly core.TopTracer_test -- -DemitVcd=1" > tracer_output.log 2>&1s

• This will dump all the logs+signature in tracer_output.log

• Update the paths to your imem and dmem in src/test/scala/core/TopTracer_test.scala
• Run the commands

sbt "testOnly core.TopTracer_test -- -DemitVcd=1" > tracer_output.log 2>&1s
awk '/Begin Logging/{flag=1; next} /End Logging/{flag=0} flag' tracer_output.log > TopTracer_clean.log
diff TopTracer_clean.log riscof/riscof_work/I/src/sb-align-01.S/ref/Reference-spike.signature

• This will compare the core's signature with any test in riscof_work dir (i.e sb-align for this case)

• Program's waveform at: build/chiselsim/TopTracer_test/Top-under-test/workdir-verilator/trace.vcd
• Clean Signature File at: TopTracer_clean.log

• Pre-Reqs: riscof pip package + spike simulator

cd riscof/
riscof arch-test --clone
riscof --verbose info run --config ./config.ini --suite ./riscv-arch-test/riscv-test-suite/rv32i_m --env ./riscv-arch-test/riscv-test-suite/env