Pinned Loading

1. asynchronous_fifo asynchronous_fifo Public

   Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.

   Verilog 40 8

2. SRAM_Controller SRAM_Controller Public template

   The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requ…

   Verilog 2

3. Uart_tx_main Uart_tx_main Public

   Uart=Stands for Universal Asynchronous Reception and Transmission (UART).A simple serial communication protocol that allows the host communicates with the auxiliary device.UART supports bi-directio…

   Verilog 2

4. memory_verification_using_system_verilog memory_verification_using_system_verilog Public

   In this respiratory having two verification methods first have without scoreboard and monitor and second with includes all component

   SystemVerilog 7 1

5. Dual_port_ram Dual_port_ram Public

   dual clock dual port ram using verilog and system verilog

   SystemVerilog 5

6. Jtag_verliog_rtl Jtag_verliog_rtl Public

   jtag tap_controller_fsm Verilog code

   Verilog 7 2