tock · KamilDuljas · Oct 19, 2025 · lschuermann · Nov 24, 2025
diff --git a/Cargo.lock b/Cargo.lock
diff --git a/Cargo.toml b/Cargo.toml
@@ -39,6 +39,7 @@ members = [
     "boards/sma_q3",
     "boards/nucleo_f429zi",
     "boards/nucleo_f446re",
+    "boards/nucleo_l476rg",
     "boards/particle_boron",
     "boards/pico_explorer_base",
     "boards/raspberry_pi_pico",
@@ -106,6 +107,8 @@ members = [
     "chips/stm32f446re",
     "chips/stm32f412g",
     "chips/stm32f4xx",
+    "chips/stm32l4xx",
+    "chips/stm32l476rg",
     "chips/veer_el2",
     "chips/virtio",
     "kernel",

diff --git a/boards/nucleo_l476rg/.cargo/config.toml b/boards/nucleo_l476rg/.cargo/config.toml
@@ -0,0 +1,14 @@
+# Licensed under the Apache License, Version 2.0 or the MIT License.
+# SPDX-License-Identifier: Apache-2.0 OR MIT
+# Copyright Tock Contributors 2024.
+
+include = [
+  "../../cargo/tock_flags.toml",
+  "../../cargo/unstable_flags.toml",
+]
+
+[build]
+target = "thumbv7em-none-eabi"
+
+[unstable]
+config-include = true
diff --git a/boards/nucleo_l476rg/Cargo.toml b/boards/nucleo_l476rg/Cargo.toml
@@ -0,0 +1,26 @@
+# Licensed under the Apache License, Version 2.0 or the MIT License.
+# SPDX-License-Identifier: Apache-2.0 OR MIT
+# Copyright Tock Contributors 2022.
+
+[package]
+name = "nucleo_l476rg"
+version.workspace = true
+authors.workspace = true
+build = "../build.rs"
+edition.workspace = true
+
+[dependencies]
+components = { path = "../components" }
+cortexm4 = { path = "../../arch/cortex-m4" }
+kernel = { path = "../../kernel" }
+stm32l476rg = { path = "../../chips/stm32l476rg" }
+
+capsules-core = { path = "../../capsules/core" }
+capsules-extra = { path = "../../capsules/extra" }
+capsules-system = { path = "../../capsules/system" }
+
+[build-dependencies]
+tock_build_scripts = { path = "../build_scripts" }
+
+[lints]
+workspace = true
diff --git a/boards/nucleo_l476rg/Makefile b/boards/nucleo_l476rg/Makefile
@@ -0,0 +1,26 @@
+# Licensed under the Apache License, Version 2.0 or the MIT License.
+# SPDX-License-Identifier: Apache-2.0 OR MIT
+# Copyright Tock Contributors 2022.
+
+# Makefile for building the tock kernel for the NUCLEO-L476RG platform
+#
+
+include ../Makefile.common
+
+OPENOCD=openocd
+
+# Default target for installing the kernel.
+.PHONY: install
+install: flash
+
+.PHONY: flash-debug
+flash-debug: $(TOCK_ROOT_DIRECTORY)target/$(TARGET)/debug/$(PLATFORM).elf
+	$(OPENOCD) -c "source [find board/st_nucleo_l4.cfg]; init; reset halt; flash write_image erase $<; verify_image $<; reset; shutdown"
+
+.PHONY: flash
+flash: $(TOCK_ROOT_DIRECTORY)target/$(TARGET)/release/$(PLATFORM).elf
+	$(OPENOCD) -c "source [find board/st_nucleo_l4.cfg]; init; reset halt; flash write_image erase $<; verify_image $<; reset; shutdown"
+
+.PHONY: program
+program: $(TOCK_ROOT_DIRECTORY)target/$(TARGET)/debug/$(PLATFORM).elf
+	$(error See README.md and update this section accordingly)
diff --git a/boards/nucleo_l476rg/chip_layout.ld b/boards/nucleo_l476rg/chip_layout.ld
@@ -0,0 +1,19 @@
+/* Licensed under the Apache License, Version 2.0 or the MIT License. */
+/* SPDX-License-Identifier: Apache-2.0 OR MIT                         */
+/* Copyright Tock Contributors 2025.                                  */
+
+/* Memory layout for the STM32L476RG
+ * rom = 512KB (LENGTH = 0x00080000)
+ * kernel = 256KB
+ * user = 256KB
+ * ram = 128KB */
+
+/* Memories definition */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x08000000, LENGTH = 0x00040000
+  prog (rx) : ORIGIN = 0x08040000, LENGTH = 0x00040000
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+}
+
+PAGE_SIZE = 2K;
diff --git a/boards/nucleo_l476rg/layout.ld b/boards/nucleo_l476rg/layout.ld
@@ -0,0 +1,6 @@
+/* Licensed under the Apache License, Version 2.0 or the MIT License. */
+/* SPDX-License-Identifier: Apache-2.0 OR MIT                         */
+/* Copyright Tock Contributors 2025.                                  */
+
+INCLUDE ./chip_layout.ld
+INCLUDE tock_kernel_layout.ld
diff --git a/boards/nucleo_l476rg/src/io.rs b/boards/nucleo_l476rg/src/io.rs
@@ -0,0 +1,97 @@
+// Licensed under the Apache License, Version 2.0 or the MIT License.
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+// Copyright Tock Contributors 2022.
+
+use core::fmt::Write;
+use core::panic::PanicInfo;
+use core::ptr::{addr_of, addr_of_mut};
+
+use kernel::debug;
+use kernel::debug::IoWrite;
+use kernel::hil::led;
+use kernel::hil::uart;
+use kernel::hil::uart::Configure;
+
+use stm32l476rg::chip_specs::Stm32l476Specs;
+use stm32l476rg::gpio::PinId;
+
+use crate::CHIP;
+use crate::PROCESSES;
+use crate::PROCESS_PRINTER;
+
+/// Writer is used by kernel::debug to panic message to the serial port.
+pub struct Writer {
+    initialized: bool,
+}
+
+/// Global static for debug writer
+pub static mut WRITER: Writer = Writer { initialized: false };
+
+impl Writer {
+    /// Indicate that USART has already been initialized. Trying to double
+    /// initialize USART2 causes STM32xxxx to go into in in-deterministic state.
+    pub fn set_initialized(&mut self) {
+        self.initialized = true;
+    }
+}
+
+impl Write for Writer {
+    fn write_str(&mut self, s: &str) -> ::core::fmt::Result {
+        self.write(s.as_bytes());
+        Ok(())
+    }
+}
+
+impl IoWrite for Writer {
+    fn write(&mut self, buf: &[u8]) -> usize {
+        let rcc = stm32l476rg::rcc::Rcc::new();
+        let clocks: stm32l476rg::clocks::Clocks<Stm32l476Specs> =
+            stm32l476rg::clocks::Clocks::new(&rcc);
+        let uart = stm32l476rg::usart::Usart::new_usart2(&clocks);
+
+        if !self.initialized {
+            self.initialized = true;
+
+            let _ = uart.configure(uart::Parameters {
+                baud_rate: 115200,
+                stop_bits: uart::StopBits::One,
+                parity: uart::Parity::None,
+                hw_flow_control: false,
+                width: uart::Width::Eight,
+            });
+        }
+
+        for &c in buf {
+            uart.send_byte(c);
+        }
+        buf.len()
+    }
+}
+
+/// Panic handler.
+#[panic_handler]
+pub unsafe fn panic_fmt(info: &PanicInfo) -> ! {
+    // User LD2 is connected to PA05
+    // Have to reinitialize several peripherals because otherwise can't access them here.
+    let rcc = stm32l476rg::rcc::Rcc::new();
+    let clocks: stm32l476rg::clocks::Clocks<Stm32l476Specs> =
+        stm32l476rg::clocks::Clocks::new(&rcc);
+    let syscfg = stm32l476rg::syscfg::Syscfg::new(&clocks);
+    let exti = stm32l476rg::exti::Exti::new(&syscfg);
+    let pin = stm32l476rg::gpio::Pin::new(PinId::PA05, &exti);
+    let gpio_ports = stm32l476rg::gpio::GpioPorts::new(&clocks, &exti);
+    pin.set_ports_ref(&gpio_ports);
+    let led = &mut led::LedHigh::new(&pin);
+
+    let writer = &mut *addr_of_mut!(WRITER);
+
+    debug::panic(
+        &mut [led],
+        writer,
+        info,
+        &cortexm4::support::nop,
+        PROCESSES.unwrap().as_slice(),
+        &*addr_of!(CHIP),
+        &*addr_of!(PROCESS_PRINTER),
+    )
+}