Parameterized N×N output-stationary systolic array accelerator for INT8 neural network inference. Full RTL-to-GDS flow on ASAP7 7nm using Cadence Genus + Innovus. 667 MHz, 42.7 GOPS peak throughput, 0.33 mW/GOP. SystemVerilog RTL, synthesis, place-and-route and self-checking testbench included.
neural-network accelerator systemverilog vlsi cadence digital-design genus tpu physical-design innovus 7nm rtl-to-gds systolic-array asap7
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Updated
Feb 18, 2026 - Verilog