vhdl

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Here are 121 public repositories matching this topic...

cocotb / cocotb

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cocotb: Python-based chip (RTL) verification

python test vhdl verification verilog uvm

Updated Feb 21, 2026
Python

olofk / fusesoc

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Package manager and build abstraction tool for FPGA/ASIC development

python package-manager fpga vhdl eda verilog reuse

Updated Feb 13, 2026
Python

siliconcompiler / siliconcompiler

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Modular hardware build system

asic fpga hls vhdl eda rtl verilog make synthesis cmos

Updated Feb 22, 2026
Python

olofk / edalize

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An abstraction library for interfacing EDA tools

Updated Feb 18, 2026
Python

jeremiah-c-leary / vhdl-style-guide

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Style guide enforcement for VHDL

styleguide linting guide vhdl style beautify coding standard

Updated Feb 5, 2026
Python

Nic30 / hwt

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VHDL/Verilog/SystemC code generator, simulator API written in python/c++

simulator fpga compiler hls vhdl rtl verilog hcl codegenerator codegen systemverilog systemc uvm

Updated Dec 23, 2025
Python

suoto / hdl_checker

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Repurposing existing HDL tools to help writing better code

Updated Jun 6, 2024
Python

kevinpt / symbolator

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HDL symbol generator

vhdl verilog symbol hdl

Updated Feb 2, 2023
Python

Paebbels / pyVHDLParser

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Streaming based VHDL parser.

parser vhdl python-3 language-model

Updated Jul 15, 2024
Python

hdl-registers / hdl-registers

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An open-source HDL register code generator fast enough to run in real time.

python c html asic generator fpga cplusplus register vhdl eda rtl csr axi axi-lite register-interface

Updated Feb 2, 2026
Python

cocotb / cocotb-bus

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Pre-packaged testbenching tools and reusable bus interfaces for cocotb

interface bus vhdl verilog hdl testbench cocotb

Updated Feb 16, 2026
Python

oddball / ipxact2systemverilog

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Translates IPXACT XML to synthesizable VHDL or SystemVerilog

vhdl verilog ip-xact systemverilog

Updated Jan 28, 2026
Python

VHDL / pyVHDLModel

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An abstract language model of VHDL written in Python.

python dom vhdl abstract language-model

Updated Jan 28, 2026
Python

suoto / vim-hdl

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Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

productivity vhdl vim-plugins verilog xilinx syntastic syntax-checker altera systemverilog modelsim

Updated Jun 1, 2021
Python

Nic30 / hwtLib

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hardware library for hwt (= ipcore repo)

fpga vhdl rtl verilog hardware-designs

Updated Dec 23, 2025
Python

mbuesch / crcgen

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Generator for CRC HDL code (VHDL, Verilog, MyHDL)

vhdl verilog crc crc-algorithms crc-calculation crc32 myhdl

Updated Oct 13, 2023
Python

Remillard / VHDL-Mode

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A package for Sublime Text that aids coding in the VHDL language.

language emacs sublime-text vhdl

Updated Aug 18, 2023
Python

Nic30 / hdlConvertorAst

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Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

python fpga vhdl verilog codegenerator codegen systemverilog systemc

Updated Nov 12, 2025
Python

tsfpga / tsfpga

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A flexible and scalable development platform for modern FPGA projects.

asic fpga ci simulation test vhdl build-automation eda test-automation rtl verilog xilinx synthesis vivado systemverilog implementation vunit

Updated Feb 2, 2026
Python

BLu85 / AES-GCM-128-192-256-bits

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Configurable AES-GCM IP (128, 192, 256 bits)

python asic fpga vhdl aes-256 aes-128 aes-192 aes-gcm aes-encryption aes-decryption

Updated Aug 27, 2025
Python

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vhdl

Here are 121 public repositories matching this topic...

cocotb / cocotb

olofk / fusesoc

siliconcompiler / siliconcompiler

olofk / edalize

jeremiah-c-leary / vhdl-style-guide

Nic30 / hwt

suoto / hdl_checker

kevinpt / symbolator

Paebbels / pyVHDLParser

hdl-registers / hdl-registers

cocotb / cocotb-bus

oddball / ipxact2systemverilog

VHDL / pyVHDLModel

suoto / vim-hdl

Nic30 / hwtLib

mbuesch / crcgen

Remillard / VHDL-Mode

Nic30 / hdlConvertorAst

tsfpga / tsfpga

BLu85 / AES-GCM-128-192-256-bits

Improve this page

Add this topic to your repo