The PoC Library has been forked to github.com/VHDL/PoC. See new address below

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).

Portable HyperRAM controller

Expiremental Speech Recognition System using VHDL & MATLAB.

IP Core Library - Published and maintained by the Open Source VHDL Group

Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.

Simple SoC in VHDL with full toolchain and custom board.

ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)

Utilities for Avalon Memory Map

Floating point FP32 core HDL. For Xilinx FPGAs. Include base converters and some math functions.

Division Algorithms in FPGAs

FPGA implementation of the popular logic game using VHDL and Altera DE1

UART Protocol made for Altera DE2-115 FPGA in VHDL

Controle de motor DC + Sensores fim de curso implementado em VHDL para o kit DE0-CV utilizado na matéria de Elementos de sistemas do 3 semestre de Engenharia da computação do Insper.

FPGA and CPLD programming, tutorials and information I figure out.

Altera Quartus project for Altera Cyclone III FPGA boards which uses one manager board and two worker boards to sort an array of numbers in parallel.

Stopwatch implementation on a Cyclone V FPGA