🐙 A CAL Dataflow Compiler for High-Level Synthesis

Verilog RISC Processor Design

The logic files of SG1 project

Jogo implementado numa placa FPGA Altera DE2 no âmbito de Projecto de Sistemas Digitais, maioritariamente escrito em VHDL

RISC-V 1 and 5-stage CPUs Described in Chisel for Implementation in an Altera FPGA

Moon Cresta Arcade Synthesized on an Altera DE2-35 Dev Board.

Assorted Verilog that brings up different elements (VGA, Ethernet, Switches, LED, LCD, etc.) of the terasIC DE2-70 Development Board.

BASIC-52 running on Cyclone IV at 11.0592, 25 and 50 MHz. EPCS4 configuration flash. 50MHz oscillator pin 24 used. 27 MHz unused.

Nios II processor based Qsys using Altera Quartus II 18.1 using Cyclone IV FPGA EP4CE10E22C8

A collection of examples and libraries using the Altera OpenCL HLS SDK

Controle de motor DC + Sensores fim de curso implementado em VHDL para o kit DE0-CV utilizado na matéria de Elementos de sistemas do 3 semestre de Engenharia da computação do Insper.

6502, 6809 and Z80 implementation on cyclone II FPGA

Digital Systems Laboratory UIUC FA 2016

A coocbook of HDL (primarily Verilog) modules

FPGA and CPLD programming, tutorials and information I figure out.

Digital Locker implemented in Verilog HDL using a Finite State Machine (FSM). Unlocks with sequence 1010, includes simulation, RTL schematic, and documentation.

80C52 + 8kB ROM + 4kB RAM on Altera CYCLONE 10 running with BASIC-52 on 8kB ROM

Bagman Arcade synthesized on an Altera DE2-35 Dev Board.

Hybrid Cryptography on the DE1-SoC(Intel Cycle V FGPA). Simon Cipher algorithm is implemented in software and hardware. This SoC is composed of a HPS(ARM Cortex A9 800Mhz(dual core)) coupled with Intel/Altera Cyclone V FPGA.