8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

Design of a frequency synthesizer to generate the 20 GHz output signal from 100 MHz input using 𝑉𝐷𝐷 of 1.2V in Cadence 65nm CMOS process

Charge Pump PLL Modeling and Simulation. A block diagram level simulator for Capsim was written in C which allows for very fast simulations and the verification of PLL performance. The objective is to match the nonlinear mixed analog/digital PLL circuit performance with high level fast "C" modeling of the charge pump PLL.