Enhances construction site safety using YOLO for object detection, identifying hazards like workers without helmets or safety vests, and proximity to machinery or vehicles. HDBSCAN clusters safety cone coordinates to create monitored zones. Post-processing algorithms improve detection accuracy.

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

Verilog Implementation of an ARM LEGv8 CPU

A python toolbox for easily downloading and processing Sentinel-1 SLC, Sentinel-2 and DEM data.

Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.

🧠 This repository features an intelligent agent that autonomously explores the Wumpus World—a grid filled with hidden Wumpuses, pits, and gold. Using logic, inference, and planning, the agent avoids dangers, finds gold, and escapes. Includes real-time Pygame visualization and customizable settings, ideal for AI/game logic study and experimentation

An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) at UMJI.

ARM Processor, Computer Architecture laboratory, University of Tehran

A pipelined MIPS processor implemented in Verilog, featuring hazard detection and forwarding.

Augmented-Waste-Classifier-SigLIP2 is an image classification vision-language encoder model fine-tuned from google/siglip2-base-patch16-224

Python GUI-based hazard video labelling

Smart Building Evacuation Ontology

CURSO - Taller de Sistemas de Información Geográfica aplicados a Desarrollo y Ordenamiento Territorial (OT) - SIGE

A 32-bit Arm Processor Using Verilog HDL With Hazard Detection, Forwarding Unit, SRAM Memory & A 2-Way Set-Associative Cache.

Design and development of a complete RISC CPU with: five stage pipeline, forwarding, automatic hazard detection, BTB using LRU policy replacement, four-cycle hardware multiplier.

Computer organisation and architecture assignments

The Hazard Detection and Captioning System uses state-of-the-art models like YOLOv11 for object detection and BLIP-based models for caption generation to analyze driver behavior and identify hazards in video streams.

A real-time application for detecting and tracking Globally Harmonized System (GHS) hazard labels using computer vision.

Verilog Implementation of an ARM LEGv8 CPU

A 5-Stage Pipelined RISC-V Processor designed and implemented on FPGA (Artix-7 Nexys A7). Supports RV32I instructions set (R, I, S, B, U, J types) with ALU, control unit, hazard detection, forwarding, and pipeline registers. Verified through simulation and hardware testing with optimized timing and 4× performance gain.