hdl
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
Here are 67 public repositories matching this topic...
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
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Nov 26, 2025 - VHDL
Open source FPGA development platform
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Jul 31, 2023 - VHDL
Over-engineered SDR development board
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Aug 3, 2025 - VHDL
The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).
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Dec 24, 2020 - VHDL
A hardware implementation of a feed-forward Convolutional Neural Network called XNOR-Net which has faster execution due to the replacement of vector-matrix multiplication to “XNOR + Popcount” operation
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Sep 16, 2018 - VHDL
RMII interface ethernet MAC Core for 10/100 MBit ethernet implementation with support CDC and AXI-Stream BUS without management and without MDIO interface support
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Jan 21, 2022 - VHDL
Getting started with VHDL: Very High Speed Integrated Circuit Hardware Description Language.
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Oct 12, 2025 - VHDL
simple demo hardware code for implement access to ST7789 LCD display from FPGA
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Mar 28, 2022 - VHDL
A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)
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Apr 5, 2022 - VHDL
FPGA Implementation of Full Search Block matching using an asynchronous handshake based FSM.
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Nov 2, 2020 - VHDL
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