CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] | SE Semester IV | Computer Engineering

💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/

RISC-V processor core under development, focusing on RV32I RTL design and phased verification using SystemVerilog and UVM.

Balanced ternary logic SoC with CPU, memory controllers, and complete synthesis flow for silicon fabrication

Intel® Performance Counter Monitor (Intel® PCM)

Collected article documents in PDF

Lightweight recording and sampling of performance counters for specific code segments directly from your C++ application.

SST Architectural Simulation Components and Libraries

A simple 8-bit microcontroller architecture built with VHDL, using the Pomegranate design framework.

A graphical processor simulator and assembly editor for the RISC-V ISA

This repository contains the basic files for the class project of the course "Architecture of Digital Systems I"

Flote is a HDL and Python framework for simulation. Designed to be friendly, simple, and productive. Easy to use and learn.

A processor cache simulator for the MIPS architecture

A 32-bit MIPS processor in verilog

An open source processor design framework written in VHDL.

Yet another processor simulator

This repository contains my Multi-Cycle Datapath (MCDP) project designed in Logisim for my Computer Organization and Design CEP. It’s a custom processor architecture built from basic components, executing each instruction over multiple clock cycles through distinct stages.

Microprocesseur RISC/CRAPS implémenté en SHDL, conçu pour faciliter la compréhension des principes de base d'un processeur RISC grâce à un jeu d'instructions simplifié.

An Implementation of MIPS processor with single cycle architecture using Verilog.

WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]