Just a enum for ELF header e_machine field

This docker container simplify building risc-v toolchain for Ergochip processor.

Rust implementation of spike's RISC-V disassembler, spike-dasm

rv64i linux userspace no_std

🖥️ A 32-bit 5-stage scalar pipelined RISC-V processor that follows the RV32I ISA specification (ECE 411 Final Project).

Contributions from aicas to EU-funded Tristan project

RISC-V programming tasks from the course "Processor Architecture" at the University of Rostock.

Our work as students (Team Breizh Hat) for the national CVA6 softcore hackathon organized by Thales Group

Verilog 32-Bit Sequential RISC-V Processor Design

A step-by-step implementation of a RISC-V CPU using SystemVerilog, including modules for ALU operations, memory instructions, and branching. Features testbenches, assembler integration, and optional FPGA deployment for real-world testing. Perfect for exploring CPU architecture and hardware design.

CH32V003J4M6 (In progress)

Code39 Barcode Encoder written in RISC-V Asssembly language

risc-v rv32i arch functional simulator from mipt sim course

Implementation of a RISC-V CPU in SystemVerilog.

Assignment of MIT 6.1810 Operating System Engineering

Just a simple test

Lab assignments for the MYTH (Microprocessor For You in Thirty Hours) RISC-V CPU Workshop

The final project for 02155

Simple hand-rolled RTOS experiment for the HiFive1 rev B, a RISC-V development board from SiFive