A Verilog implementation of DisplayPort protocol for FPGAs

Verilog implementation of the SHA-512 hash function.

True Random Number Generator core implemented in Verilog.

Verilog implementation of the SHA-1 cryptgraphic hash function

Hardware implementation of the SHA-256 cryptographic hash function

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

SystemVerilog microarchitecture challenge for AI No.2. Adding the flow control.

Verilog AXI components for FPGA implementation

PicoRV32 - A Size-Optimized RISC-V CPU

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

A Verilog synthesis flow for Minecraft redstone circuits

SERV - The SErial RISC-V CPU

cocotb: Python-based chip (RTL) verification

GPGPU microprocessor architecture

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

A FPGA friendly 32 bit RISC-V CPU implementation

Verilator open-source SystemVerilog simulator and lint system

Icarus Verilog

Digital logic design tool and simulator

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

A minimal GPU design in Verilog to learn how GPUs work from the ground up