Implement extended precision integer addition (#607)

* Refactor emit_intrinsic to allow struct return type

* Implement extended precision integer addition

Uses `llvm.*add.with.overflow.*`. That intrinsic does not take a carry argument, so handling carry in requires multiple additions and combining the carry out, but the AMDGPU target is able to translate that pattern into a single instruction.

These four PTX instructions:

```
    add.cc.u32      r0, a0, b0;
    addc.cc.u32     r1, a1, b1;
    addc.cc.u32     r2, a2, b2;
    addc.u32        r3, a3, b3;
```

are translated into four RDNA3 instructions:

```
    v_add_co_u32 v0, vcc_lo, v0, v4
    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo
    v_add_co_ci_u32_e32 v2, vcc_lo, v2, v6, vcc_lo
    v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
```

* cargo fmt

* Rename to match convention

* cargo fmt

Host functions for vLLM (#606)

Add sad and dp2a instructions (#605)

Use partial parsing result in release mode (#603)

Fix for a regression in #569 and some minor fixes for llama.cpp on Windows

Update docs (add llama.cpp, zluda_precompile sections) (#602)

Stop failing on bf16 uint_to_fp on amdgpu < gfx11 (#601)

Add CUDA 13.1 compatibility (#599)

Also fix all the warnings

When building ZLUDA in CI, make sure we build Linux binaries compatib…

…le with both ROCm 6 and ROCm 7 (#589)

When building ZLUDA in CI, make sure we build Linux binaries compatib…

…le with both ROCm 6 and ROCm 7 (#589)

Allow implicit conversion from bit scalar to vec for st (#585)