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Commits on Jun 26, 2020

• target/arm: Enable MTE

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• target/arm: Add allocation tag storage for system mode

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• target/arm: Create tagged ram when MTE is enabled

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• target/arm: Cache the Tagged bit for a page in MemTxAttrs

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• target/arm: Always pass cacheattr to get_phys_addr

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• target/arm: Set PSTATE.TCO on exception entry

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• target/arm: Implement data cache set allocation tags

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• target/arm: Complete TBI clearing for user-only for SVE

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• target/arm: Add mte helpers for sve scatter/gather memory ops

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• target/arm: Handle TBI for sve scalar + int memory ops

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• target/arm: Add mte helpers for sve scalar + int ff/nf loads

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• target/arm: Add mte helpers for sve scalar + int stores

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• target/arm: Add mte helpers for sve scalar + int loads

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• target/arm: Add arm_tlb_bti_gp

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• target/arm: Tidy trans_LD1R_zpri

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• target/arm: Use mte_check1 for sve LD1R

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• target/arm: Use mte_checkN for sve unpredicated stores

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• target/arm: Use mte_checkN for sve unpredicated loads

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• target/arm: Add helper_mte_check_zva

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• target/arm: Implement helper_mte_checkN

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• target/arm: Implement helper_mte_check1

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• target/arm: Add gen_mte_checkN

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• target/arm: Add gen_mte_check1

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• target/arm: Move regime_tcr to internals.h

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• target/arm: Move regime_el to internals.h

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• target/arm: Implement the access tag cache flushes

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• target/arm: Implement the LDGM, STGM, STZGM instructions

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• target/arm: Simplify DC_ZVA

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• target/arm: Restrict the values of DCZID.BS under TCG

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• target/arm: Implement the STGP instruction

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• target/arm: Implement LDG, STG, ST2G instructions

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• target/arm: Define arm_cpu_do_unaligned_access for user-only

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• target/arm: Implement the SUBP instruction

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• target/arm: Implement the GMI instruction

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• target/arm: Implement the ADDG, SUBG instructions

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