This project implements a 4-point, 8-bit fixed-point Fast Fourier Transform (FFT) engine using SystemVerilog, designed to be deployed on TinyTapeout through the TT PCB. The FFT engine is based on a radix-2 decimation-in-time (DIT) architecture, structured in two stages using butterfly modules and twiddle factor multiplication to compute the frequency-domain representation of four complex time-domain samples.

The system interfaces with users through a simple control scheme consisting of 8 input switches, bidirectional I/O pins, and a single-digit 7-segment display. Switches 0 and 1 control the data flow into and out of the system, respectively.

• Authors: Mariam ElSahhar, Hadi Zaidi
• Architecture: 4-point FFT using radix-2 decimation-in-time with butterfly units
• Input/Output: 8-bit complex samples (full 8-bit real and imaginary components)
• Clock: 50 MHz
• Processing Time: 20 clock cycles

Used to interface with control switches

Used to interface with 7-segment display

• Input Mode uio_in[7:0]: Used to input samples
• Output Mode uio_out[7:0]: Used to output frequency bins
• Output Enable uio_oe[7:0]: Indicates whether pins are inputting/outputting

• Reset rst_n: Active low reset
• Clock clk: System timing (50 MHz)

1. Load Phase: Input 4 complex samples sequentially via data bus
2. Processing: FFT computation (20 cycles)
3. Output Phase: Read 4 complex FFT results sequentially

The 7-segment display shows the current operation mode throughout the process.

• Technical Documentation - Detailed architecture and operation
• Test Plan - Pre-silicon testing strategy
• INITIAL Google Doc, outdated now only kept to show initial arch/diagrams

See the test directory README for detailed instructions on running pre-silicon tests.

cd test

# Run individual module tests
make test-butterfly     # Test butterfly computation units
make test-fft-engine   # Test core FFT engine
make test-memory       # Test memory controller
make test-io           # Test I/O controller
make test-top          # Test complete system

# Run all tests
make all

# Gate-level simulation (after synthesis)
make test-top GATES=yes

# Create a virtual environment
python3 -m venv fft_test_env

#Activate the virtual environment

# Install required packages
cd test
pip install -r requirements.txt

# Run full system test
make test-top

# Or run all tests
make all

deactivate