Thanks for the contribution.

Please can you separate the changes here into two commits:

• adding C5 support
• adding the new board

@dpgeorge
Thank you for your reply. It has now been revised.

@AZKKXL #17971 When this PR ends, this automatic reading problem may be avoided, and he will not ask for XTAL frequency at compile time.

@Vincent1-python WOW! That's cool!

@projectgus OK,I resolved conversation : )

Compiled with a no-name ESP3C5 board using esp-idf v5.5.1. At first, the firmware was too large for the factory partition, ~32k overflow. SO I added the line below to sdkconfig.board, which reduces the firmware size by about 90k. The line does not have any impact on performance.

CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y

@AZKKXL the esp32 port now uses IDF v5.5.1, so this C5 support should work.

Can you please rebase this on latest master?

@AZKKXL the esp32 port now uses IDF v5.5.1, so this C5 support should work.

Can you please rebase this on latest master?

Already rebase.

Code size report:

Reference:  esp32/esp32_rmt: Update RMT module to use the new RMT API. [2a3b9b0]
Comparison: tools/ci.sh: Build ESP32_GENERIC_C5 as part of esp32 CI. [merge of 336d463]
  mpy-cross:    +0 +0.000% 
   bare-arm:    +0 +0.000% 
minimal x86:    +0 +0.000% 
   unix x64:    +0 +0.000% standard
      stm32:    +0 +0.000% PYBV10
     mimxrt:    +0 +0.000% TEENSY40
        rp2:    +0 +0.000% RPI_PICO_W
       samd:    +0 +0.000% ADAFRUIT_ITSYBITSY_M4_EXPRESS
  qemu rv32:    +0 +0.000% VIRT_RV32

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 98.38%. Comparing base (2a3b9b0) to head (336d463).
⚠️ Report is 3 commits behind head on master.

@@           Coverage Diff           @@
##           master   #17912   +/-   ##
=======================================
  Coverage   98.38%   98.38%           
=======================================
  Files         171      171           
  Lines       22294    22294           
=======================================
  Hits        21933    21933           
  Misses        361      361           

☔ View full report in Codecov by Sentry.
📢 Have feedback on the report? Share it here.

@AZKKXL Something went wrong when you rebased (it had 255 commits showing in the PR). I've rebased again and squashed down to one commit so we can re-review.

If you need to make any more local changes then you'll need to reset your local branch to match this remote branch, first. (To do this, run git fetch origin and then git reset --hard origin/seeed_xiao_esp32c5 - but you will lose any other local changes you have in the branch!!)

n

I apologize for only seeing this now due to personal reasons. Could you confirm if the current submission format is correct? If not, please let me know. I will pay close attention to this in the coming days and strive to complete this PR.

I tested building the new ESP32_GENERIC_C5 board, and it doesn't build due to two reasons:

• error with redefinition of CONFIG_XTAL_FREQ
• firmware is too big to fit in flash

For the first problem, I suggest dynamically calculating the I2C bus frequency using (in machine_i2c.c):

@@ -263,7 +263,13 @@ static void machine_hw_i2c_init(machine_hw_i2c_obj_t *self, bool first_init) {
         .master.clk_speed = self->freq,
     };
     i2c_param_config(self->port, &conf);
-    int timeout = i2c_ll_calculate_timeout_us_to_reg_val(I2C_SCLK_FREQ, self->timeout_us);
+    #if CONFIG_IDF_TARGET_ESP32C5
+    uint32_t i2c_sclk_freq;
+    check_esp_err(esp_clk_tree_src_get_freq_hz(I2C_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &i2c_sclk_freq));
+    #else
+    uint32_t i2c_sclk_freq = I2C_SCLK_FREQ;
+    #endif
+    int timeout = i2c_ll_calculate_timeout_us_to_reg_val(i2c_sclk_freq, self->timeout_us);
     i2c_set_timeout(self->port, (timeout > I2C_LL_MAX_TIMEOUT) ? I2C_LL_MAX_TIMEOUT : timeout);
     i2c_driver_install(self->port, I2C_MODE_MASTER, 0, 0, 0);
 }

For the second problem, include the boards/sdkconfig.riscv fragment in the SDKCONFIG_DEFAULTS list of files.

Oh, and I think a dependencies lock file needs to be added for C5 as well.

Oh, and I think a dependencies lock file needs to be added for C5 as well.

Sorry, could we ask you to handle the maintenance of this after merging the PR later?

OK, I've now added to this PR the following:

• fix I2C build on C5
• add dependencies lockfile for esp32c5
• add ESP32_GENERIC_C5 to the CI, to test that it builds