pub struct Mode0Port<SPI: 'static, EN: 'static, M: RawMutex + 'static> { /* private fields */ }Trait Implementations§
Source§impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode0, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode0, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
async fn into_configured_port( self, config: ConfigMode0, ) -> Result<MaxPort<ConfigMode0, SPI, EN, M>, Error<S, P>>
Source§impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode1, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode1, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
async fn into_configured_port( self, config: ConfigMode1, ) -> Result<MaxPort<ConfigMode1, SPI, EN, M>, Error<S, P>>
Source§impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode10, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode10, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
async fn into_configured_port( self, config: ConfigMode10, ) -> Result<MaxPort<ConfigMode10, SPI, EN, M>, Error<S, P>>
Source§impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode11, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode11, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
async fn into_configured_port( self, config: ConfigMode11, ) -> Result<MaxPort<ConfigMode11, SPI, EN, M>, Error<S, P>>
Source§impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode12, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode12, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
async fn into_configured_port( self, config: ConfigMode12, ) -> Result<MaxPort<ConfigMode12, SPI, EN, M>, Error<S, P>>
Source§impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode2, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode2, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
async fn into_configured_port( self, config: ConfigMode2, ) -> Result<MaxPort<ConfigMode2, SPI, EN, M>, Error<S, P>>
Source§impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode3, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode3, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
async fn into_configured_port( self, config: ConfigMode3, ) -> Result<MaxPort<ConfigMode3, SPI, EN, M>, Error<S, P>>
Source§impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode4, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode4, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
async fn into_configured_port( self, config: ConfigMode4, ) -> Result<MaxPort<ConfigMode4, SPI, EN, M>, Error<S, P>>
Source§impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode5, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode5, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
async fn into_configured_port( self, config: ConfigMode5, ) -> Result<MaxPort<ConfigMode5, SPI, EN, M>, Error<S, P>>
Source§impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode6, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode6, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
async fn into_configured_port( self, config: ConfigMode6, ) -> Result<MaxPort<ConfigMode6, SPI, EN, M>, Error<S, P>>
Source§impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode7, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode7, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
async fn into_configured_port( self, config: ConfigMode7, ) -> Result<MaxPort<ConfigMode7, SPI, EN, M>, Error<S, P>>
Source§impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode8, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode8, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
async fn into_configured_port( self, config: ConfigMode8, ) -> Result<MaxPort<ConfigMode8, SPI, EN, M>, Error<S, P>>
Source§impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode9, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
impl<SPI, EN, M, S, P> IntoConfiguredPort<ConfigMode9, SPI, EN, M, S, P> for Mode0Port<SPI, EN, M>
async fn into_configured_port( self, config: ConfigMode9, ) -> Result<MaxPort<ConfigMode9, SPI, EN, M>, Error<S, P>>
Auto Trait Implementations§
impl<SPI, EN, M> Freeze for Mode0Port<SPI, EN, M>
impl<SPI, EN, M> !RefUnwindSafe for Mode0Port<SPI, EN, M>
impl<SPI, EN, M> Send for Mode0Port<SPI, EN, M>
impl<SPI, EN, M> Sync for Mode0Port<SPI, EN, M>
impl<SPI, EN, M> Unpin for Mode0Port<SPI, EN, M>
impl<SPI, EN, M> UnsafeUnpin for Mode0Port<SPI, EN, M>
impl<SPI, EN, M> !UnwindSafe for Mode0Port<SPI, EN, M>
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more