This reverts commit a9cf8fd.

This reverts commit ae976e5.

This reverts commit 09fb5b7.

This reverts commit 4b3a42f.

This reverts commit 6b3e82f.

This reverts commit 6e35786.

Add binding for Sophgo SG2042 PCIe host controller.

Reviewed-by: Rob Herring (Arm) <[email protected]>
Signed-off-by: Chen Wang <[email protected]>
Link: https://lore.kernel.org/r/2755f145755b6096247c26852b63671a6fea4dbf.1757643388.git.unicorn_wang@outlook.com
Signed-off-by: Han Gao <[email protected]>

ops of struct cdns_pcie may be NULL, direct use
will result in a null pointer error.

Add checking of pcie->ops before using it for new
driver that may not supply pcie->ops.

Signed-off-by: Chen Wang <[email protected]>
Link: https://lore.kernel.org/r/35182ee1d972dfcd093a964e11205efcebbdc044.1757643388.git.unicorn_wang@outlook.com
Signed-off-by: Han Gao <[email protected]>

Add support for PCIe controller in SG2042 SoC. The controller
uses the Cadence PCIe core programmed by pcie-cadence*.c. The
PCIe controller will work in host mode only, supporting data
rate (16 GT/s) and lanes (x16 or x8).

Signed-off-by: Chen Wang <[email protected]>
Link: https://lore.kernel.org/r/01b0a57cd9dba8bed7c1f2d52997046c2c6f042b.1757643388.git.unicorn_wang@outlook.com
Signed-off-by: Han Gao <[email protected]>

Add PCIe controller nodes in DTS for Sophgo SG2042.
Default they are disabled.

Signed-off-by: Inochi Amaoto <[email protected]>
Signed-off-by: Chen Wang <[email protected]>
Link: https://lore.kernel.org/r/828860951ec4973285fe92fceb4b6f0ecb365a2f.1757643388.git.unicorn_wang@outlook.com
Signed-off-by: Han Gao <[email protected]>

Enable PCIe controllers for PioneerBox, which uses SG2042 SoC.

Signed-off-by: Chen Wang <[email protected]>
Link: https://lore.kernel.org/r/a499a1c17f317ea57de8769032ec65e1e18b4b36.1757643388.git.unicorn_wang@outlook.com
Signed-off-by: Han Gao <[email protected]>

Enable PCIe controllers for Sophgo SG2042_EVB_V1.X board,
which uses SG2042 SoC.

Signed-off-by: Chen Wang <[email protected]>
Link: https://lore.kernel.org/r/76d4012e515dc3c3d4e406a237eadc55203f77b6.1757643388.git.unicorn_wang@outlook.com
Signed-off-by: Han Gao <[email protected]>

Enable PCIe controllers for Sophgo SG2042_EVB_V2.0 board,
which uses SG2042 SoC.

Signed-off-by: Chen Wang <[email protected]>
Link: https://lore.kernel.org/r/16831a3277a6c8c19436a17ac199d2f9b80f9ce5.1757643388.git.unicorn_wang@outlook.com
Signed-off-by: Han Gao <[email protected]>

…EVB_V2"

This reverts commit 72c3cae.

…EVB_V1"

This reverts commit 64b1794.

…Box"

This reverts commit b047f5b.

This reverts commit d0deeee.

Add SPI NOR controller node for SG2042

Reviewed-by: Chen Wang <[email protected]>
Tested-by: Chen Wang <[email protected]>
Signed-off-by: Zixian Zeng <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Han Gao <[email protected]>

Enable SPI NOR node for PioneerBox device tree

According to PioneerBox schematic, SPI-NOR Flash cannot support QSPI
due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1.

Reviewed-by: Chen Wang <[email protected]>
Tested-by: Chen Wang <[email protected]>
Signed-off-by: Zixian Zeng <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Han Gao <[email protected]>

Enable SPI NOR node for SG2042_EVB_V1 device tree

According to SG2042_EVB_V1 schematic, SPI-NOR Flash cannot support QSPI
due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1.

Signed-off-by: Zixian Zeng <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Han Gao <[email protected]>

Enable SPI NOR node for SG2042_EVB_V2 device tree

According to SG2042_EVB_V2 schematic, SPI-NOR Flash cannot support QSPI
due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1.

Signed-off-by: Zixian Zeng <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Han Gao <[email protected]>