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riscv64: add sg2042 support #3

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Merged
merged 34 commits into from
Jun 4, 2025
Merged

riscv64: add sg2042 support #3

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9cbfe73
FROMLIST: dt-bindings: pci: Add Sophgo SG2042 PCIe host
unicornx Jun 4, 2025
9aee9bf
FROMLIST: PCI: sg2042: Add Sophgo SG2042 PCIe driver
unicornx Jun 4, 2025
fe5df3d
FROMLIST: dt-bindings: mfd: syscon: Add sg2042 pcie ctrl compatible
unicornx Jun 4, 2025
b0b0320
FROMLIST: riscv: sophgo: dts: add pcie controllers for SG2042
unicornx Jun 4, 2025
7e5c394
FROMLIST: riscv: sophgo: dts: enable pcie for PioneerBox
unicornx Jun 4, 2025
1b8cc1f
UPSTREAM: riscv: dts: sophgo: sg2042: add pinctrl support
inochisa Feb 11, 2025
8e36c96
UPSTREAM: riscv: sophgo: dts: Add spi controller for SG2042
sycamoremoon Jun 4, 2025
588773e
FROMLIST: dt-bindings: net: sophgo,sg2044-dwmac: Add support for Soph…
inochisa Jun 4, 2025
189ed9f
FROMLIST: net: stmmac: dwmac-sophgo: Add support for Sophgo SG2042 SoC
inochisa Jun 4, 2025
62fcb41
FROMLIST: net: stmmac: platform: Add snps,dwmac-5.00a IP compatible s…
inochisa Jun 4, 2025
a265b9d
FROMLIST: riscv: dts: sophgo: add ethernet GMAC device for sg2042
inochisa Jun 4, 2025
bf4830d
FROMLIST: riscv: Move vendor errata definitions into vendorid_list.h
guoren83 Jun 4, 2025
3529cdf
FROMLIST: riscv: qspinlock: errata: Add ERRATA_THEAD_WRITE_ONCE fixup
guoren83 Jun 4, 2025
9320d35
FROMLIST: riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
RevySR Jun 4, 2025
b831f19
FROMLIST: riscv: dts: sophgo: add ziccrse for sg2042
RevySR Jun 4, 2025
695ca3a
FROMLIST: riscv: dts: sophgo: add zfh for sg2042
RevySR Jun 4, 2025
2486164
FROMLIST: dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X bindings
RevySR Jun 4, 2025
a0446d8
FROMLIST: riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device…
RevySR Jun 4, 2025
c9c9ce0
FROMLIST: dt-bindings: riscv: add Sophgo SG2042_EVB_V2.0 bindings
RevySR Jun 4, 2025
b0f2362
FROMLIST: riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device…
RevySR Jun 4, 2025
17b8671
FROMLIST: riscv: vector: Fix context save/restore with xtheadvector
RevySR Jun 4, 2025
74fa466
FROMLIST: spi: dt-bindings: spi-sg2044-nor: Add SOPHGO SG2042
sycamoremoon Jun 4, 2025
dbfcc8d
FROMLIST: mtd: spi-nor: Add GD25LB512ME GigaDevice flash_info
sycamoremoon Jun 4, 2025
56bb2bd
FROMLIST: riscv: dts: sophgo: Add SPI NOR node for SG2042
sycamoremoon Jun 4, 2025
87eadda
SOPHGO: riscv: kexec: Add image loader for kexec file
xingxg2022 Jun 4, 2025
f35d9ca
REVYOS: pcie: sg2042: pcie_rc1 use msi as msi-parent
RevySR Jun 4, 2025
7768115
REVYOS: dts: sophgo: sg2042: move pcie domain config into board devic…
inochisa Jun 4, 2025
6c4c38f
REVYOS: dts: sophgo: sg2042: add pcie port for sg2042 EVB V1.X/V2.0
inochisa Jun 4, 2025
3eb11eb
REVYOS: riscv: dts: sophgo: enable pcie_rc for Sophgo SG2042_EVB_V1.X
RevySR Jun 4, 2025
805efed
REVYOS: riscv: dts: sophgo: enable pcie_rc for Sophgo SG2042_EVB_V2.0
RevySR Jun 4, 2025
af08386
REVYOS: riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1/V2
RevySR Jun 4, 2025
43234a6
RISCV64: REVYOS: dts: sophgo: sg2042: sync old kernel numa-id
RevySR Jun 4, 2025
a6f9777
RISCV64: REVYOS: Revert "riscv: Enable pcpu page first chunk allocator"
RevySR Jun 4, 2025
a20a0b7
RISCV64: REVYOS: Revert "NUMA: early use of cpu_to_node() returns 0 i…
RevySR Jun 4, 2025
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FROMLIST: mtd: spi-nor: Add GD25LB512ME GigaDevice flash_info 
Add GD25LB512ME SPI-NOR flash information.

The following SFDP dump was generated after applying the current commit.

------------------------------------------------------------------------
This flash is populated on the SG2042 Pioneer board and was tested at
100MHz frequency using the spi-sg2044-nor SPI controller.

root@localhost ~ # cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
gd25lb512me
root@localhost ~ # cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c8671a
root@localhost ~ # cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
gigadevice
root@localhost ~ # xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
53464450060102ff00060110300000ffc8000103900000ff84000102c000
00ffffffffffffffffffffffffffffffffffe520eaffffffff1f44eb086b
003b00bbfeffffffffff00ffffff44eb0c200f5210d800ffd531b1fe83d6
1458ec6006337a757a7504bdd55c2906740008500001ffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffff002050169df9
8156d9c8ffffffffffffffffffffffffffffffffffffffffffffffffffff
fffffffffffffffffffffffff38ff0ff215cdcff
root@localhost ~ # sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
859eb314b0500aa3e3dc5a1ad514f1013387c7aaa40147ed2d616ffc4b6d851c  /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
root@localhost ~ # #Dump debugfs data
root@localhost ~ # cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
 1S-1S-1S
  opcode	0x13
  mode cycles	0
  dummy cycles	0
 1S-1S-4S
  opcode	0x6c
  mode cycles	0
  dummy cycles	8
 1S-4S-4S
  opcode	0xec
  mode cycles	2
  dummy cycles	4
 4S-4S-4S
  opcode	0xec
  mode cycles	2
  dummy cycles	4

Supported page program modes by the flash
 1S-1S-1S
  opcode	0x12
 1S-1S-4S
  opcode	0x34
 1S-4S-4S
  opcode	0x3e
root@localhost ~ # cat /sys/kernel/debug/spi-nor/spi0.0/params
name		gd25lb512me
id		c8 67 1a ff c8 67
size		64.0 MiB
write size	1
page size	256
address nbytes	4
flags		HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_16BIT_SR | SOFT_RESET

opcodes
 read		0x13
  dummy cycles	0
 erase		0x21
 program	0x12
 8D extension	none

protocols
 read		1S-1S-1S
 write		1S-1S-1S
 register	1S-1S-1S

erase commands
 21 (4.00 KiB) [1]
 5c (32.0 KiB) [2]
 dc (64.0 KiB) [3]
 c7 (64.0 MiB)

sector map
 region (in hex)   | erase mask | overlaid
 ------------------+------------+----------
 00000000-03ffffff |     [ 1  ] | no
root@localhost ~ # dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.1 MB, 2.0 MiB) copied, 0.0279486 s, 75.0 MB/s
root@localhost ~ # mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
root@localhost ~ # mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
root@localhost ~ # hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
root@localhost ~ # sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5  spi_read
root@localhost ~ # mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
root@localhost ~ # mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
root@localhost ~ # sha256sum spi*
a2ebfaebe38974847a4efb628b29a72f1d50e78c17318869d8954b033dc32e5d  spi_read
a2ebfaebe38974847a4efb628b29a72f1d50e78c17318869d8954b033dc32e5d  spi_test
root@localhost ~ # mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 67108864 (64M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0

Signed-off-by: Zixian Zeng <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Han Gao <[email protected]>
  • Loading branch information
@sycamoremoon @RevySR
sycamoremoon authored and RevySR committed Jun 4, 2025
commit dbfcc8d1b03b506ef7fd33a095bc0f1a3e213ccc
17 changes: 17 additions & 0 deletions drivers/mtd/spi-nor/gigadevice.c
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Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,15 @@ static const struct spi_nor_fixups gd25q256_fixups = {
.post_bfpt = gd25q256_post_bfpt,
};

static void gd25lb512me_default_init(struct spi_nor *nor)
{
nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
}

static const struct spi_nor_fixups gd25lb512me_fixups = {
.default_init = gd25lb512me_default_init,
};

static const struct flash_info gigadevice_nor_parts[] = {
{
.id = SNOR_ID(0xc8, 0x40, 0x15),
Expand Down Expand Up @@ -82,6 +91,14 @@ static const struct flash_info gigadevice_nor_parts[] = {
.size = SZ_16M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
}, {
.id = SNOR_ID(0xc8, 0x67, 0x1a),
.name = "gd25lb512me",
.size = SZ_64M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
.fixups = &gd25lb512me_fixups,
.fixup_flags = SPI_NOR_4B_OPCODES,
},
};

Expand Down