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ChiselVerify: A Hardware Verification Library for Chisel

In this repository, we proprose ChiselVerify, which is the begining of a verification library within Scala for digital hardware described in Chisel, but also upporting legacy components in VHDL, Verilog, or SystemVerilog. The library runs off of ChiselTest for all of the DUT interfacing.

A technical report describes the library in detail: Open-Source Verification with Chisel and Scala.

When you use this library in a research project, please cite it as:

@INPROCEEDINGS{ChiselVerify:2021,
  author = {Andrew Dobis and Tjark Petersen and Hans Jakob Damsgaard and Kasper
	Juul Hesse Rasmussen and Enrico Tolotto and Simon Thye Andersen and
	Richard Lin and Martin Schoeberl},
  title = {ChiselVerify: An Open-Source Hardware Verification Library for Chisel
	and Scala},
  booktitle = {2021 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP
	and International Symposium of System-on-Chip (SoC)},
  year = {2021}
}

ChiselVerify is published on Maven. To use it, add following line to your build.sbt:

libraryDependencies += "io.github.chiselverify" % "chiselverify" % "0.2.0"

Run tests with

make

This README contains a brief overview of the library and its functionalities. For a more in-depth tutorial, please check-out the ChiselVerify Wiki. Ohter general documentation, such as technical reports and conference papers, can be found in the documentation repository.

Verification Library for Chisel

The library can be divided into 3 main parts:

  1. Functional Coverage: Enabling Functional Coverage features like Cover Points, Cross Coverage, Timed Coverage and Conditional Coverage.
  2. Constrained Random Verification: Allowing for constraints and random variables to be defined and used directly in Scala.
  3. Bus Functional Models: Enabling Transactional modeling for standardized Buses like AXI4.

Functional Coverage in Chisel

The idea is to implement functional coverage features directly in Chisel.
The structure of the system can be seen in the diagram below.

Structure of the Coverage system

Coverage Reporter

This is the heart of the system. It handles everything from registering the Cover Points to managing the Coverage DataBase. It will also generate the final coverage report. Registering Cover Points together will group them into a same Cover Group.

Coverage DB

This DataBase handles the maintenance of the values that were sampled for each of the Cover Point bins. This allows us to know how much of the verification plan was tested.
The DB also keeps mappings linking Cover Groups to their contained Cover Points.

How to use it

The Functional coverage system is compatible with the chisel testers2 framework.

  1. The CoverageReporter must first be instanciated within a chisel test.
  2. CoverGroups can then be created by using the register method of the coverage reporter. This takes as parameter a List[Cover]. Cover represents either a CoverPoint or a CoverCondition that contains a port that will be sampled, a portName that will be shown in the report and either a List[Bins], created from a name and a scala range, or a List[Condition], created from a name and an arbitrary condition function.
  3. CoverGroups may also contain a List[Cross] which represents a set of hit relations between two ports.
  4. The port must then be manually sampled by calling the sample method of the coverage reporter.
  5. Once the test is done, a coverage report can be generated by calling the printReport or report methods of the coverage reporter.

An example of this can be found here.

Timed Cross Coverage

Idea: We want to check the relationship between two ports with a delay of a certain amount of cycles.
Example: We have the following situation, imagine we have a device that breaks if:

  • dut.io.a takes the value of 1.U at cycle 1
  • dut.io.b takes the value of 1.U the following cycle

We want to verify that the above case was tested. This can be done by defining a TimedCross between the two points:

val cr = new CoverageReporter(dut)
cr.register(
      //Declare CoverPoints
      cover("a", dut.io.a)(DefaultBin(dut.io.a))),
      cover("b", dut.io.b)(DefaultBin(dut.io.b))),
      //Declare timed cross point with a delay of 1 cycle
      cover("timedAB", dut.io.a, dut.io.b)(Exactly(1))(
            cross("both1", Seq(1 to 1, 1 to 1))
      )
)

Using that, we can check that we tested the above case in our test suite.
This construct can be used to check delay between two cover points.

Use

To be able to use the timed coverage, stepping the clock must be done through the coverage reporter:

dut.clock.step(nCycles) //Will trigger an exception if used with Timed Cross Coverage
cr.step(nCycles) //Works

This is done in order ensure that the coverage database will always remain synchronized with the DUT's internal clock.

Delay Types

The current implementation allows for the following special types of timing:

  • Eventually: This sees if a cross hit was detected at any point in the next given amount of cycles.
  • Always: This only considers a hit if the it was detected every cycle in the next given amount of cycles.
  • Exactly: This only considers a hit if it was detected exactly after a given amount of cycles.

Timed Assertions

Delay types can also be used in order to used Timed Assertions or Timed Expect. These can be used in order to check an assertion, in the form of an arbitrary function, with an added timing argument. We could thus check, for example, that two ports are equal two cycles appart. For example:

AssertTimed(dut, dut.io.a.peek() === dut.io.b.peek(), "aEqb expected timing is wrong")(Exactly(2)).join()

This can also be done more naturally with the Expect interface:

ExpectTimed(dut,dut.io.a, dut.io.b.peek().litValue(), "aEqb expected timing is wrong")(Exactly(2)).join()

These can also be used with a simplyfied syntax, inspired by ScalaTest syntax:

//For Timed Assertions
eventually(2, "aEqb expected timing is wrong") { dut.io.a.peek() === dut.io.b.peek() }
exact(2, "aEqb expected timing is wrong") { dut.io.a.peek() === dut.io.b.peek() }
always(2, "aEqb expected timing is wrong") { dut.io.a.peek() === dut.io.b.peek() }
never(2, "aEqb expected timing is wrong") { dut.io.a.peek() === dut.io.b.peek() }

Example use case

Here is a toy example of how to use the assertion:

always(9, "a isn't always less than or equal to one") { LtEq(dut.io.outB, dut.io.outA) }
always(9, "a isn't always greater than or equal to one") { GtEq(dut.io.outB, dut.io.outA) }

Cover Conditions

Idea: A type of coverpoint that can apply arbitrary hit conditions to an arbitrary number of ports.

cover(readableName: String, ports: Data*)(conditions: Condition*)
//where a condition is declared using the bin function without a range
bin(name: String, func : Seq[BigInt] => Boolean)

Example:

val cr = new CoverageReporter(dut)
cr.register(
  //Declare CoverPoints
  cover("aAndB", dut.io.outA, dut.io.outB)(
    bin("aeqb", { case Seq(a, b) => a == b })
))

Bins are thus defined using arbitrary functions of the type List[BigInt] => Boolean which represent different hit conditions. No coverage percentage is given due to cartesian product complexity. Instead we offer the possibility to use a user-defined "expected number of Hits" to get a coverage percentage. This looks like the following:

val cr = new CoverageReporter(dut)
cr.register(
  //Declare CoverPoints
  cover("aAndB", dut.io.outA, dut.io.outB)(
    bin("asuptobAtLeast100Times", condition = { case Seq(a, b) => a > b }, expectedHits = 100)
))

The above example results in the following coverage report:

============ COVERAGE REPORT ============
============== GROUP ID: 1 ==============
COVER_CONDITION NAME: aAndB
CONDITION aeqb HAS 4 HITS
CONDITION asuptobAtLeast100 HAS 95 HITS EXPECTED 100 = 95.0%
=========================================
=========================================

Constrained Random Verification

The CRV package inside this project aims to mimic the functionality of SystemVerilog constraint programming and integrates them into ChiselTest. The CRV package combines a Constraint Satisfactory Problem Solver, with some helper classes to create and use random objects inside your tests. Currently, only the jacop backend is supported, but in the future other backends can be added.

Comparison

System Verilog

class frame_t;
rand pkt_type ptype;
rand integer len;
randc bit [1:0] no_repeat;
// Constraint the members
constraint legal {
  len >= 2;
  len <= 5;
}

CRV / jacop backend

class Frame extends RandObj(new Model) {
  val pkType: RandVar = rand(0, 3)
  val len: RandVar = rand(0, 10)
  val noRepeat: RandVar = rand(0, 1, Cyclic)

  val legal: ConstraintGroup = new ConstraintGroup {
    len >= 2
    len <= 5
  }
}

Random Objects

Random objects can be created by extending the RandObj trait. This class accepts one parameter which is a Model. A model correspond to a database in which all the random variables and constraints declared inside the RandObj are stored.

class Frame extends RandObj(new Model)

A model can be initialized with a seed new Model(42), which allows the user to create reproducible tests.

Random Fields

Random fields are defined using the following function:

def rand(min: Int, max: Int, randType: RandType = Normal)(implicit model: Model): RandVar

A random field can be added to a RandObj by declaring a Rand variable.

  val len: RandVar = rand(0, 10)

Random-cyclic variable can be added by declaring a Randc field inside a RandObj. This is done using the Cyclic RandType parameter.

  val noRepeat: RandVar = rand(0, 1, Cyclic)

Constraints

Each variable can have one or multiple constraints. These are defined using constraint operators.

len >= 2

In the previous block of code we are specifying that the variable len can only take values that are grater then 2. Each constraint can be assigned to a variable and enabled or disabled at any time during the test

val lenConstraint = len > 2
[....]
lenConstraint.disable()
[....]
lenConstraint.enable()

Constraints can also be grouped together in a ConstraintGroup and the group itself can be enabled or disabled.

val legal: ConstraintGroup = new ConstraintGroup {
  len >= 2
  len <= 5
  payload.size == len
}
[...]
legal.disable()
[...]
legal.enable()

By default, constraints and constraint groups are enabled when they are declared.

The list of operator used to construct constraints is the following: <, <=, >, >=,==, div, *, mod, +, -, \=, ^, in, inside.

It is also possible to declare conditional constraints with constructors like IfCon and IfElseCon.

val constraint1: crv.Constraint = IfCon(len == 1) {
        payload.size == 3
    } ElseC {
        payload.size == 10
    }

Usage

As in SystemVerilog, each random class exposes a method called randomize() this method automatically solves the constraint specified in the class and assign to each random filed a random value. The method returns true only if the CSP found a set of values that satisfy the current constraints.

val myPacket = new Frame(new Model)
assert(myPacket.randomize)

Other usage examples can be found in our backend tests.

Example Use Cases

We will explore a handful of use cases to explore verification.

UVM Examples

In the early stages of this project, we explored the possibilty of using UVM to verify Chisel designs. The sv directory thus contains a number of UVM examples.

Simple examples

In sv/uvm-simple-examples a number of simple examples are located. These start with a very basic testbench with no DUT attached, and gradually transition into a complete testbench.

Vivado UVM Examples

These examples assume that a copy of Xilinx Vivado is installed and present in the PATH. The examples are currently tested only on Linux.

Leros ALU

In the directory sv/leros, the Leros ALU is tested using UVM, to showcase that Chisel and UVM can work together. This testbench is reused to also test a VHDL implementation of the ALU, to show that UVM is usable on mixed-language designs (when using a mixed-language simulator).

The VHDL implementaion is run by setting the makefile argument TOP=top_vhd.

Using the SV DPI and Javas JNI

Using the SystemVerilog DPI (Direct Programming Interface) to cosimulate with a golden model described in C is explored in the scoreboard_dpi.svh file. The C-model is implemented in scoreboard.c, and the checking functionality is called from the SystemVerilog code.

Implementing a similar functionality in Scala/Chisel has been explored via the JNI (Java Native Interface). In the directory native, the necessary code for a simple Leros tester using the JNI is implemented.

To use the JNI functionality, first run make jni to generate the correct header files and shared libraries. Then, open sbt and type project native to access the native project. Then run sbt test to test the Leros ALU using a C model called from within Scala. To switch back, type project chisel-uvm.

Resources

If you're interested in learning more about the UVM, we recommend that you explore the repository, as well as some of the following links:

Documents

Collect pointers to relevant documents.

Related Work

Fuzzing

Here are a few pointers to some interesting documentation around the topic of mutation-based fuzzing:

CRV

  • Choco-Solver Java library for solving CSP problems
  • QuickCheck Checker for Haskel, used Lava as example, the inspiration for ScalaCheck

Testing Framewrok / Simulation tools

Cocotb -- coroutine based cosimulation python library library for hardware development in Python

Cocotb repository: cocotb is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.

Resources Related to Cocotb

Extension of Cocotb

  • cocotb-coverage: Extension that enables coverage and constrained random verification
    • Publication in iEEE Paper
  • python-uvm: port of SystemVerilog (SV) Universal Verification Methodology (UVM) 1.2 to Python and cocotb

Hwt -- Python library for hardware development

hwt: one of the golas of this library is to implement some simulation feature similar to UVM

Not strictly relevant resources

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