- xilinx runtime (xrt)
- compiler(vitis v++)
- the code was tested on U50: https://www.xilinx.com/products/boards-and-kits/alveo/u50.html#gettingStarted
- Change the makefile line 47 PLATFORM to your own: https://github.com/CortexFoundation/cvm-runtime/blob/fpga/Makefile#L47
- make fpga
- make test_model_fpga && ./build/tests/test_model_fpga