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96f4003
Adding an access_region tool
iansseijelly Jul 30, 2024
41666ef
FIX: default access region values
iansseijelly Aug 16, 2024
f74c632
FORMAT: Access Region tools
iansseijelly Aug 16, 2024
3590f1f
ADD: Reuse Pattern Tool Initial Commit
iansseijelly Aug 16, 2024
048ddc0
ADD: options to create reuse pattern tool
iansseijelly Aug 16, 2024
6014432
ADD: Mirgae Initial commit
iansseijelly Aug 16, 2024
c3d03a4
ADD: Fully supporting all ADD modes
iansseijelly Aug 17, 2024
06b01cb
RENAME: mir_op.h -> mir_opc.h
iansseijelly Aug 17, 2024
6070f3e
FIX: slightly smarter get type
iansseijelly Aug 17, 2024
0c97302
ADD: insn and opnd definition
iansseijelly Aug 17, 2024
6c530a8
ADD: using linked list for chained mir in a single drir
iansseijelly Aug 17, 2024
b94fb08
Merge branch 'DynamoRIO:master' into access_pattern
iansseijelly Aug 17, 2024
34b7d22
ADD: linked list implementation
iansseijelly Aug 18, 2024
3e922fd
ADD: major refactor for individualized register operation in gen_ops
iansseijelly Aug 18, 2024
0f9d8b7
FIX: CMake include
iansseijelly Aug 19, 2024
7e95684
ADD: development on generating mir_insn for memref types
iansseijelly Aug 20, 2024
de2bdb7
ADD: temporarily adding print for debugging
iansseijelly Aug 20, 2024
b7d7643
ADD: mir memref composition
iansseijelly Aug 20, 2024
1b68d54
FIX: removing redundant header def
iansseijelly Aug 20, 2024
8fb4f2a
FIX: strdup for correct insn print
iansseijelly Aug 20, 2024
69358fc
ADD: proper handling for store, subject to change
iansseijelly Aug 20, 2024
a5f385d
FIX: setting correct opcodes to addr calc
iansseijelly Aug 20, 2024
d755ba0
FIX: changing the store representation to save 1 instruction
iansseijelly Aug 20, 2024
dba42fe
ADD: Generalizing arith ops
iansseijelly Aug 20, 2024
e91e70f
ADD: temp reg allocation and fixing pc-relative addressing
iansseijelly Aug 21, 2024
0d4f797
ADD: change store encoding + adding push op (WIP)
iansseijelly Aug 21, 2024
fe51787
ADD: pop operation
iansseijelly Aug 21, 2024
a08951b
REFACTOR: Use static mir_opnd_t instead of dynamically allocation
iansseijelly Aug 23, 2024
76c6ece
Merge branch 'DynamoRIO:master' into access_pattern
iansseijelly Aug 23, 2024
8327781
FIX: renaming fe to frontend for clarity
iansseijelly Aug 26, 2024
b88f9a8
FIX: minor fix to update CMake include path
iansseijelly Aug 26, 2024
55ed02b
ADD: mov and call
iansseijelly Sep 3, 2024
e123028
FIX: print hex for mir imm opnds if large
iansseijelly Sep 3, 2024
b792ce0
ADD: lea opcode
iansseijelly Sep 3, 2024
016fc28
ADD: support for flag setting and supressing jump
iansseijelly Sep 3, 2024
95858a6
ADD: support for shift left and right
iansseijelly Sep 3, 2024
8570c13
FIX: printing flags properly
iansseijelly Sep 8, 2024
0e0f3bc
ADD: nop for unwanted instructions
iansseijelly Sep 8, 2024
659bc21
ADD: basic replayer backend
iansseijelly Sep 10, 2024
10fc010
FIX: adding stubs to call replayer from tools
iansseijelly Sep 10, 2024
be94e8a
ADD: basic replayer test
iansseijelly Sep 10, 2024
ed31e38
ADD: more tests for movs and different adds
iansseijelly Sep 11, 2024
33447cf
ADD: basic reg testing, and testplans
iansseijelly Sep 11, 2024
550f38e
ADD: tmp regfile tests
iansseijelly Sep 11, 2024
93205a2
FIX: reverting the flag register logic
iansseijelly Sep 11, 2024
1e90f2a
ADD: test for memory operations
iansseijelly Sep 11, 2024
4b5fe4d
ADD: logging load store in a hardcoded file
iansseijelly Sep 11, 2024
b48e640
ADD: handling variable length registers
iansseijelly Sep 11, 2024
70f1930
FIX: wrong lea opcode format
iansseijelly Sep 11, 2024
0148792
ADD: APIs in frontend to handle variable register length alias
iansseijelly Sep 11, 2024
25b98f4
ADD: support RET operation
iansseijelly Sep 11, 2024
148fddd
TEXT: check off the test plan todo list
iansseijelly Sep 11, 2024
0121325
FIX: renaming abstract_backend
iansseijelly Sep 12, 2024
0836c4a
ADD: basic register dependency analyzer
iansseijelly Sep 12, 2024
94bc3bc
FIX: minor replayer fixes
iansseijelly Sep 12, 2024
9cf3f86
ADD: addr with index and scale for stride
iansseijelly Sep 23, 2024
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FIX: minor replayer fixes
  • Loading branch information
iansseijelly committed Sep 12, 2024
commit 94bc3bc90e1e6d49528f524b167e47e6c9090438
5 changes: 5 additions & 0 deletions clients/drcachesim/mirage/backend/replayer.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -67,6 +67,7 @@ void Replayer::step(mir_insn_t *insn) {
dst_val = src0_val + src1_val;
set_val_to_opnd(insn->dst, dst_val);
break;
// FIXME: check directionality!!
case MIR_OP_SUB:
dst_val = src0_val - src1_val;
set_val_to_opnd(insn->dst, dst_val);
Expand All @@ -83,6 +84,10 @@ void Replayer::step(mir_insn_t *insn) {
dst_val = src0_val % src1_val;
set_val_to_opnd(insn->dst, dst_val);
break;
case MIR_OP_AND:
dst_val = src0_val & src1_val;
set_val_to_opnd(insn->dst, dst_val);
break;
case MIR_OP_OR:
dst_val = src0_val | src1_val;
set_val_to_opnd(insn->dst, dst_val);
Expand Down
5 changes: 2 additions & 3 deletions clients/drcachesim/mirage/backend/replayer.h
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
using std::unordered_map;

#include "dr_api.h"
#include "abstract_replayer.h"
#include "abstract_backend.h"
#include "translate_context.h"
#include "mir_insn.h"

Expand All @@ -14,12 +14,11 @@ enum InitStrategy {
INIT_STRATEGY_RANDOM
};

class Replayer : public AbstractReplayer {
class Replayer : public AbstractBackend {
public:
Replayer(InitStrategy init_strategy);
~Replayer();
void replay(mir_insn_list_t *insn_list) override;

// this is public for testing purposes
uint64_t get_reg_val(reg_id_t reg);
private:
Expand Down