AXI MMCM Phase Controller

This repository contains a lightweight AXI4-Lite slave that sequences the Clocking Wizard MMCM dynamic phase-shift interface (psclk, psen, psincdec, psdone).

PG065 review notes

The implementation is based on doc/pg065-clk-wiz.pdf:

• Dynamic phase shift is exposed on the Clocking Wizard through psclk, psen, psincdec, and psdone in the product guide port table.
• Dynamic phase shift is available only when the inferred/generated primitive is an MMCM. The guide's feature table marks it unsupported for PLL and BUFGCE_DIV.
• The Output Clocks configuration requires Use Fine PS to be enabled for any output that must respond to dynamic phase-shift commands.
• The full Clocking Wizard AXI4-Lite reconfiguration path is intended for frequency, phase, and duty-cycle register programming and carries a significantly larger logic footprint. This controller avoids that path and only automates the fine phase-step handshake.

Delivered RTL

rtl/axi_clk_wiz_phase_ctrl.v provides:

• A 32-bit AXI4-Lite slave.
• A signed STEP_COUNT register. Positive values increment phase, negative values decrement phase.
• A CONTROL register with a software-visible output-clock select field and a start bit.
• A STATUS register with busy, done, error, locked, active target, and remaining steps.
• Direct outputs for psclk, psen, and psincdec, with psclk tied to s_axi_aclk.
• Sticky interrupt generation on done or error.

Register map

• 0x00 CONTROL
  • bit[0]: start (write 1 to launch a transaction)
  • bit[10:8]: phase_target_sel
  • bit[16]: irq_enable
• 0x04 STATUS
  • bit[0]: busy
  • bit[1]: done sticky, write 1 back to clear
  • bit[2]: error sticky, write 1 back to clear
  • bit[3]: synchronized clk_wiz_locked
  • bit[4]: sampled psdone
  • bit[5]: active psincdec
  • bit[10:8]: active target
  • bit[31:16]: steps remaining
• 0x08 STEP_COUNT
  • Signed 32-bit phase-step request.
• 0x0C APPLIED
  • Signed copy of the last accepted step request.
• 0x10 INFO
  • 0x0001_000N, where N is NUM_OUTPUTS.

Integration notes

• Configure the Clocking Wizard for MMCM mode and enable Dynamic Phase Shift.
• Enable Use Fine PS on the output clock that software intends to phase adjust.
• phase_target_sel and phase_target_onehot are exported so software can keep track of which output clock it believes it is adjusting. The MMCM fine phase-shift pins are global control inputs, so independent runtime phase control still depends on how the upstream Clocking Wizard instance is configured.
• phase_target_sel and phase_target_onehot do not connect to a Clocking Wizard clock-select port, because no such runtime select port exists on the MMCM fine phase-shift interface. Treat them as bookkeeping/debug outputs unless you add external wrapper logic that uses them.
• s_axi_aclk is reused as psclk. Keep that clock within the MMCM dynamic phase-shift timing limits for your device family.

Verification

tb/axi_clk_wiz_phase_ctrl_tb.v is a self-checking simulation that:

• writes AXI registers,
• requests positive and negative phase-step sequences,
• emulates psdone,
• verifies pulse counts, target selection, status, and interrupt behavior.

IP packaging

scripts/package_ip.tcl packages the controller as a Vivado IP repository entry under ip_repo/axi_clk_wiz_phase_ctrl_1_0.

The packaged IP explicitly marks these families as supported:

• artix7 Production
• spartanuplus Production