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@sunnyqgg sunnyqgg commented Nov 6, 2025

Summary by CodeRabbit

  • New Features

    • Added speculative decoding optimizations for Blackwell architecture with custom attention mask preparation
    • Introduced layer index tracking for multi-layer attention operations
    • Extended attention metadata to support per-key-value head configuration and speculative decoding tree masking
  • Tests

    • Added comprehensive unit tests for custom mask preparation functionality

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@sunnyqgg sunnyqgg requested review from a team as code owners November 6, 2025 13:31
@sunnyqgg sunnyqgg requested review from 2ez4bz, QiJune and byshiue November 6, 2025 13:31
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📝 Walkthrough

Walkthrough

Extends TensorRT-LLM's attention operators to support Blackwell-generation GPU spec-decoding tree masking and layer indexing. Introduces three new tensor buffers for spec-decoding (tree mask offset, tree mask, and sparse mask offset) and propagates layer indices throughout the stack—from high-level attention operations through low-level FMHA kernels. Adds a new custom mask preparation pipeline with CUDA kernels while maintaining backward compatibility for existing dense attention paths.

Changes

Cohort / File(s) Summary
Spec-Decoding Parameters and Layer Index
cpp/tensorrt_llm/common/attentionOp.h, cpp/tensorrt_llm/common/attentionOp.cpp, cpp/tensorrt_llm/kernels/decoderMaskedMultiheadAttention/xqaParams.h
Adds layer_idx scalar and three new pointers (spec_decoding_bl_tree_mask_offset, spec_decoding_bl_tree_mask, spec_bl_tree_first_sparse_mask_offset_kv) to EnqueueGenerationParams and XQAParams. Propagates parameters from generationsParams to xqaParams and extends toString() for diagnostics.
FMHA Kernel Selection and Configuration
cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h, cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaRunnerParams.h
Adds spec-decoding conditional logic for kernel type selection (KeepsMmaAbForGeneration vs. SwapsMmaAbForGeneration), custom mask preparation pre-kernel call, max heads sizing (128 for spec-decoding), and hash-based kernel selection. Relaxes constness on mask pointers and adds layer_idx, is_spec_dec_tree, and spec_decoding_generation_lengths fields.
Custom Mask Preparation Pipeline
cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.h, cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu
New CUDA kernels and host launchers for mask buffer computation and offset prefix-sum (prepareCustomMaskBuffersKernelForKeepsMmaAb, computeCustomMaskOffsetsKernel). Orchestrates two-step mask preparation via runPrepareCustomMask with error handling and validation.
Dispatcher and Kernel Integration
cpp/tensorrt_llm/kernels/xqaDispatcher.cpp, cpp/tensorrt_llm/thop/attentionOp.cpp
Enables spec-decoding support by switching mask type from Dense to Custom when active, propagates is_spec_dec_tree flag, and populates new spec-decoding runner parameters (generalPackedCustoMaskPtr, custom mask offsets). Conditional SM100-family path accepts six-tensor spec-decoding contract.
PyTorch Attention Backend
tensorrt_llm/_torch/attention_backend/interface.py, tensorrt_llm/_torch/attention_backend/trtllm.py, tensorrt_llm/_torch/pyexecutor/model_engine.py
Adds num_heads_per_kv to AttentionMetadata, extends TrtllmAttentionWrapper and metadata with three new spec-decoding tensor fields, SM version–aware spec-decoding gating, and custom mask tile computation. Propagates parameters through plan/run paths for SM >= 100.
Test Infrastructure
cpp/tests/unit_tests/kernels/CMakeLists.txt, cpp/tests/unit_tests/kernels/prepareCustomMaskTest.cpp, tests/unittest/_torch/modeling/test_modeling_llama.py
Adds comprehensive unit test for custom mask preparation (CPU reference, GPU execution, stream management) with SM100-gated skip, and updates modeling tests with num_heads_per_kv, relaxed tolerances, get_sm_version() guards, and explicit metadata preparation calls.

Sequence Diagram(s)

sequenceDiagram
    participant AttentionOp as Attention Op
    participant XQADispatcher as XQA Dispatcher
    participant FmhaKernels as FMHA Kernels
    participant PrepareCustomMask as Custom Mask Prep
    participant MmaKernel as MMA Kernel

    AttentionOp->>AttentionOp: layer_idx propagation
    AttentionOp->>XQADispatcher: enqueue with spec_decoding params
    
    alt isSpecDecoding && multi_query_tokens
        XQADispatcher->>XQADispatcher: set mask_type = Custom<br/>is_spec_dec_tree = true
        XQADispatcher->>FmhaKernels: configure runner params<br/>(layer_idx, is_spec_dec_tree,<br/>generalPackedCustoMaskPtr, etc.)
        FmhaKernels->>FmhaKernels: select KeepsMmaAbForGeneration<br/>(if mNumHeadsQPerKv ≤ 16)<br/>or SwapsMmaAbForGeneration
        FmhaKernels->>FmhaKernels: set maxNumHeadsQPerKvInCta = 128
        FmhaKernels->>PrepareCustomMask: runPrepareCustomMask()<br/>(layer_idx == 0)
        
        rect rgba(135, 206, 250, 0.3)
            note over PrepareCustomMask: Custom Mask Preparation<br/>(for spec-decoding trees)
            PrepareCustomMask->>PrepareCustomMask: launch computeCustomMaskOffsetsKernel<br/>(BlockScan prefix-sum offsets)
            PrepareCustomMask->>PrepareCustomMask: launch prepareCustomMaskBuffersKernel<br/>(compute mask buffers with atomics)
        end
        
        FmhaKernels->>MmaKernel: run with Custom mask<br/>keepsMmaAb config
    else
        XQADispatcher->>XQADispatcher: set mask_type = Dense
        FmhaKernels->>MmaKernel: run with Dense mask
    end
Loading

Estimated code review effort

🎯 4 (Complex) | ⏱️ ~60 minutes

  • fmhaKernels.h: Conditional kernel type selection logic with multiple branches for spec-decoding vs. standard paths; requires understanding of tile sizing, head counts, and kernel dispatch strategy.
  • prepareCustomMask.cu: New CUDA kernels with atomic operations, BlockScan prefix-sum, and batch indexing; requires careful verification of grid/block configurations and memory access patterns.
  • trtllm.py: Extensive changes across multiple methods (plan, run, forward, spec-decoding prep logic) with SM version gating; multi-path state management increases cognitive load.
  • xqaDispatcher.cpp: Parameter propagation and conditional mask type switching; interacts with multiple layers and requires tracing data flow.
  • Coordination across layers: New parameters flow through attentionOp → xqaDispatcher → fmhaKernels → custom mask kernels; changes in one layer depend on corresponding updates in others, increasing overall verification complexity.

Pre-merge checks and finishing touches

❌ Failed checks (2 warnings)
Check name Status Explanation Resolution
Description check ⚠️ Warning The PR description is incomplete and does not follow the required template. The Description and Test Coverage sections are empty, and the PR checklist boxes are unchecked (except a generic checkbox), leaving critical information about implementation details, tests, and verification steps undocumented. Complete the Description section explaining the implementation approach, rationale, and changes. Populate the Test Coverage section with specific tests that validate the tree attention support. Check the PR Checklist items to confirm guideline compliance, test coverage, and documentation updates.
Docstring Coverage ⚠️ Warning Docstring coverage is 32.61% which is insufficient. The required threshold is 80.00%. You can run @coderabbitai generate docstrings to improve docstring coverage.
✅ Passed checks (1 passed)
Check name Status Explanation
Title check ✅ Passed The title '[TRTLLM-8778][feat] Add tree attention support for blackwell arch' clearly summarizes the main change: adding tree attention support for Blackwell architecture. It follows the prescribed format and is specific enough to understand the primary objective.
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Actionable comments posted: 1

Caution

Some comments are outside the diff and can’t be posted inline due to platform limitations.

⚠️ Outside diff range comments (2)
tensorrt_llm/_torch/attention_backend/trtllm.py (1)

1397-1455: Set num_heads_per_kv before allocating BL custom mask buffers

TrtllmAttentionMetadata.num_heads_per_kv still equals its dataclass default (1) by the time spec_decoding_param_prepare_for_blackwell() runs. For multi-/group-query configs the actual heads-per-KV ratio is >1, so mask_size is undercomputed and the GPU kernel will write past the allocated mask, corrupting memory. Please populate metadata.num_heads_per_kv from the wrapper before you call metadata.update_spec_dec_param(...).

         self.wrapper.plan(
             layer_idx=self.get_local_layer_idx(metadata),
             tokens_per_block=metadata.tokens_per_block,
             max_num_requests=metadata.max_num_requests,
@@
             sparse_attn_indices=sparse_attn_indices,
             sparse_attn_offsets=sparse_attn_offsets,
             sparse_mla_topk=metadata.sparse_mla_topk if hasattr(
                 metadata, 'sparse_mla_topk') else 0)
+        if metadata.num_heads_per_kv is None:
+            metadata.num_heads_per_kv = self.wrapper.num_heads // max(
+                self.wrapper.num_kv_heads, 1)
tensorrt_llm/_torch/pyexecutor/model_engine.py (1)

912-950: Uninitialized num_heads_per_kv can crash metadata setup

num_heads_per_kv is only assigned inside the if self.model.model_config.pretrained_config.num_attention_heads is not None block, yet it is unconditionally passed into self.attn_backend.Metadata(...). For any config that omits num_attention_heads (or sets it to None), _set_up_attn_metadata now raises UnboundLocalError, breaking model initialization and inference. Please default num_heads_per_kv before the conditional (e.g., to 1) and only overwrite it when both head counts are available.

-        if self.model.model_config.pretrained_config.num_attention_heads is not None:
-            if self.model.model_config.pretrained_config.num_key_value_heads is not None:
-                num_heads_per_kv = self.model.model_config.pretrained_config.num_attention_heads // self.model.model_config.pretrained_config.num_key_value_heads
-            else:
-                num_heads_per_kv = 1
+        pretrained_cfg = self.model.model_config.pretrained_config
+        num_attention_heads = getattr(pretrained_cfg, "num_attention_heads", None)
+        num_key_value_heads = getattr(pretrained_cfg, "num_key_value_heads", None)
+        if num_attention_heads is not None and num_key_value_heads:
+            num_heads_per_kv = num_attention_heads // num_key_value_heads
+        else:
+            num_heads_per_kv = 1
🧹 Nitpick comments (2)
cpp/tensorrt_llm/thop/attentionOp.cpp (1)

520-526: Drop the raw printf in hot path.

This printf will spam stdout on every speculative decode run and bypasses the project’s logging framework. Please remove it or switch to the existing logging macros before landing.

cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu (1)

184-194: Check CUDA API return codes.

The new runtime allocates and zeroes device memory with raw CUDA calls, but none of the return values are validated. If cudaMallocAsync or cudaMemsetAsync fails under pressure, we will consume an invalid pointer and crash inside the subsequent kernels. Please wrap these calls with TLLM_CUDA_CHECK (or equivalent) so failures are caught immediately and surfaced upstream.

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📒 Files selected for processing (15)
  • cpp/tensorrt_llm/common/attentionOp.cpp (4 hunks)
  • cpp/tensorrt_llm/common/attentionOp.h (1 hunks)
  • cpp/tensorrt_llm/kernels/decoderMaskedMultiheadAttention/xqaParams.h (3 hunks)
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h (4 hunks)
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaRunnerParams.h (3 hunks)
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu (1 hunks)
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.h (1 hunks)
  • cpp/tensorrt_llm/kernels/xqaDispatcher.cpp (3 hunks)
  • cpp/tensorrt_llm/thop/attentionOp.cpp (2 hunks)
  • cpp/tests/unit_tests/kernels/CMakeLists.txt (1 hunks)
  • cpp/tests/unit_tests/kernels/prepareCustomMaskTest.cpp (1 hunks)
  • tensorrt_llm/_torch/attention_backend/interface.py (1 hunks)
  • tensorrt_llm/_torch/attention_backend/trtllm.py (9 hunks)
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  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h
  • cpp/tensorrt_llm/thop/attentionOp.cpp
  • cpp/tensorrt_llm/kernels/xqaDispatcher.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaRunnerParams.h
  • cpp/tensorrt_llm/common/attentionOp.h
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  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h
  • cpp/tensorrt_llm/thop/attentionOp.cpp
  • cpp/tensorrt_llm/kernels/xqaDispatcher.cpp
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**/*.py

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**/*.py: Python code must target Python 3.8+.
Indent Python code with 4 spaces; do not use tabs.
Maintain module namespace when importing; prefer 'from package.subpackage import foo' then 'foo.SomeClass()' instead of importing the class directly.
Python filenames should be snake_case (e.g., some_file.py).
Python classes use PascalCase names.
Functions and methods use snake_case names.
Local variables use snake_case; prefix 'k' for variables that start with a number (e.g., k_99th_percentile).
Global variables use upper SNAKE_CASE prefixed with 'G' (e.g., G_MY_GLOBAL).
Constants use upper SNAKE_CASE (e.g., MY_CONSTANT).
Avoid shadowing variables from an outer scope.
Initialize all externally visible members of a class in the constructor.
Prefer docstrings for interfaces that may be used outside a file; comments for in-function or file-local interfaces.
Use Google-style docstrings for classes and functions (Sphinx-parsable).
Document attributes and variables inline so they render under the class/function docstring.
Avoid reflection when a simpler, explicit approach suffices (e.g., avoid dict(**locals()) patterns).
In try/except, catch the most specific exceptions possible.
For duck-typing try/except, keep the try body minimal and use else for the main logic.

Files:

  • tensorrt_llm/_torch/pyexecutor/model_engine.py
  • tensorrt_llm/_torch/attention_backend/interface.py
  • tensorrt_llm/_torch/attention_backend/trtllm.py
  • tests/unittest/_torch/modeling/test_modeling_llama.py
🧠 Learnings (33)
📓 Common learnings
Learnt from: eopXD
Repo: NVIDIA/TensorRT-LLM PR: 6767
File: cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp:0-0
Timestamp: 2025-08-15T06:46:53.813Z
Learning: In the TensorRT-LLM KV cache manager, SWA (Sliding Window Attention) combined with beam search is currently in a broken/non-functional state and is planned for future rework. During preparatory refactoring phases, code related to SWA+beam search may intentionally remain in a non-working state until the broader rework is completed.
Learnt from: MatthiasKohl
Repo: NVIDIA/TensorRT-LLM PR: 6904
File: tensorrt_llm/_torch/attention_backend/trtllm.py:259-262
Timestamp: 2025-08-14T15:43:23.107Z
Learning: In TensorRT-LLM's attention backend, tensor parameters in the plan() method are assigned directly without validation (dtype, device, contiguity checks). This maintains consistency across all tensor inputs and follows the pattern of trusting callers to provide correctly formatted tensors.
Learnt from: MatthiasKohl
Repo: NVIDIA/TensorRT-LLM PR: 6904
File: cpp/tensorrt_llm/pybind/thop/bindings.cpp:55-57
Timestamp: 2025-08-14T15:38:01.771Z
Learning: In TensorRT-LLM Python bindings, tensor parameter collections like mla_tensor_params and spec_decoding_tensor_params are kept as required parameters without defaults to maintain API consistency, even when it might affect backward compatibility.
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 7104
File: cpp/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/epilogue/fusion/sm90_visitor_scatter.hpp:399-417
Timestamp: 2025-08-21T21:48:35.135Z
Learning: CUTLASS extensions in TensorRT-LLM (located under cpp/tensorrt_llm/cutlass_extensions/) are designed to integrate with and extend functionality in the external CUTLASS repository. When analyzing these extensions, their consumers and functionality wiring may exist in the CUTLASS codebase rather than within TensorRT-LLM itself.
Learnt from: eopXD
Repo: NVIDIA/TensorRT-LLM PR: 6767
File: cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp:0-0
Timestamp: 2025-08-15T06:46:54.897Z
Learning: In cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp addToken function, newly allocated blocks are unshared by design. The beam search path in addToken (when sequence.getNumTokens() > windowSize) is currently broken/non-functional with SWA, so the block allocation doesn't follow a shared-then-unshared pattern.
Learnt from: thorjohnsen
Repo: NVIDIA/TensorRT-LLM PR: 6910
File: cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp:0-0
Timestamp: 2025-08-14T21:04:50.248Z
Learning: In KV cache onboarding logic during prefill in cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp, when calculating which blocks fall within the attention window, use getTokensPerBlock() to advance token indices rather than block->getUniqueTokens().size(), because the calculation needs to consider the post-prefill state where blocks will be filled to capacity, not their current token count.
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/thop/allreduceOp.cpp:352-446
Timestamp: 2025-09-23T15:12:38.312Z
Learning: In TensorRT-LLM NCCL device implementation, NCCL version 2.28+ requirements are handled at runtime in the nccl_device/config layer rather than with compile-time guards. This allows the allreduceOp to remain version-agnostic and delegates version compatibility validation to the appropriate lower-level components that can gracefully handle unsupported configurations.
Learnt from: yechank-nvidia
Repo: NVIDIA/TensorRT-LLM PR: 6254
File: tensorrt_llm/_torch/pyexecutor/model_engine.py:1201-1204
Timestamp: 2025-07-22T09:22:14.726Z
Learning: In TensorRT-LLM's multimodal processing pipeline, shared tensor recovery using `from_shared_tensor()` is only needed during the context phase. Generation requests reuse the already-recovered tensor data and only need to call `strip_for_generation()` to remove unnecessary multimodal data while preserving the recovered tensors. This avoids redundant tensor recovery operations during generation.
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/multimem.h:20-30
Timestamp: 2025-09-23T15:13:48.819Z
Learning: TRT-LLM targets modern CUDA toolkits that support FP8 datatypes, so cuda_fp8.h can be included unconditionally without version guards in TRT-LLM code.
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/config.cu:42-49
Timestamp: 2025-09-23T14:58:05.372Z
Learning: In TensorRT-LLM NCCL device kernels (cpp/tensorrt_llm/kernels/nccl_device/), the token partitioning intentionally uses ceil-like distribution (same token_per_rank for all ranks) to ensure all ranks launch the same number of blocks. This is required for optimal NCCL device API barrier performance, even though it may launch extra blocks for non-existent tokens on later ranks. Runtime bounds checking in the kernel (blockID validation) handles the overshoot cases.
📚 Learning: 2025-09-23T15:13:48.819Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/multimem.h:20-30
Timestamp: 2025-09-23T15:13:48.819Z
Learning: TRT-LLM targets modern CUDA toolkits that support FP8 datatypes, so cuda_fp8.h can be included unconditionally without version guards in TRT-LLM code.

Applied to files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.h
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu
📚 Learning: 2025-09-23T15:01:00.070Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/config.cu:15-17
Timestamp: 2025-09-23T15:01:00.070Z
Learning: In TensorRT-LLM NCCL device kernels, the <sstream> header is not needed as an explicit include in config.cu because it's provided transitively through other headers. Local compilation testing confirms this works without the explicit include.

Applied to files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.h
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu
📚 Learning: 2025-08-14T15:43:23.107Z
Learnt from: MatthiasKohl
Repo: NVIDIA/TensorRT-LLM PR: 6904
File: tensorrt_llm/_torch/attention_backend/trtllm.py:259-262
Timestamp: 2025-08-14T15:43:23.107Z
Learning: In TensorRT-LLM's attention backend, tensor parameters in the plan() method are assigned directly without validation (dtype, device, contiguity checks). This maintains consistency across all tensor inputs and follows the pattern of trusting callers to provide correctly formatted tensors.

Applied to files:

  • cpp/tensorrt_llm/common/attentionOp.cpp
  • cpp/tensorrt_llm/thop/attentionOp.cpp
  • tensorrt_llm/_torch/attention_backend/trtllm.py
📚 Learning: 2025-08-14T21:04:50.248Z
Learnt from: thorjohnsen
Repo: NVIDIA/TensorRT-LLM PR: 6910
File: cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp:0-0
Timestamp: 2025-08-14T21:04:50.248Z
Learning: In KV cache onboarding logic during prefill in cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp, when calculating which blocks fall within the attention window, use getTokensPerBlock() to advance token indices rather than block->getUniqueTokens().size(), because the calculation needs to consider the post-prefill state where blocks will be filled to capacity, not their current token count.

Applied to files:

  • cpp/tensorrt_llm/common/attentionOp.cpp
  • tensorrt_llm/_torch/pyexecutor/model_engine.py
  • tensorrt_llm/_torch/attention_backend/interface.py
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h
  • cpp/tensorrt_llm/thop/attentionOp.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu
  • tensorrt_llm/_torch/attention_backend/trtllm.py
  • cpp/tensorrt_llm/common/attentionOp.h
  • tests/unittest/_torch/modeling/test_modeling_llama.py
📚 Learning: 2025-08-14T15:38:01.771Z
Learnt from: MatthiasKohl
Repo: NVIDIA/TensorRT-LLM PR: 6904
File: cpp/tensorrt_llm/pybind/thop/bindings.cpp:55-57
Timestamp: 2025-08-14T15:38:01.771Z
Learning: In TensorRT-LLM Python bindings, tensor parameter collections like mla_tensor_params and spec_decoding_tensor_params are kept as required parameters without defaults to maintain API consistency, even when it might affect backward compatibility.

Applied to files:

  • cpp/tensorrt_llm/common/attentionOp.cpp
  • cpp/tensorrt_llm/thop/attentionOp.cpp
  • cpp/tensorrt_llm/kernels/xqaDispatcher.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaRunnerParams.h
  • tensorrt_llm/_torch/attention_backend/trtllm.py
  • cpp/tensorrt_llm/common/attentionOp.h
  • cpp/tensorrt_llm/kernels/decoderMaskedMultiheadAttention/xqaParams.h
📚 Learning: 2025-09-29T15:14:28.503Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 8063
File: tensorrt_llm/lora_manager.py:1080-1112
Timestamp: 2025-09-29T15:14:28.503Z
Learning: In tensorrt_llm/lora_manager.py, when calculating part_sizes for attn_qkv fused LoRA modules, the sizes are correctly multiplied by tp_size because model_config.num_heads and model_config.num_kv_heads are already divided by tp_size (per-TP-rank values), so multiplication is needed to get the original full concatenated dimension size. The interleave_fused_lora_weights_for_tp function provides proper validation with asserts for total size and TP divisibility.

Applied to files:

  • cpp/tensorrt_llm/common/attentionOp.cpp
  • tensorrt_llm/_torch/pyexecutor/model_engine.py
  • cpp/tensorrt_llm/thop/attentionOp.cpp
📚 Learning: 2025-09-29T15:14:28.503Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 8063
File: tensorrt_llm/lora_manager.py:1080-1112
Timestamp: 2025-09-29T15:14:28.503Z
Learning: In tensorrt_llm/lora_manager.py, when calculating part_sizes for attn_qkv fused LoRA modules, the sizes are correctly multiplied by tp_size because model_config.num_heads and model_config.num_kv_heads are already divided by tp_size (per-TP-rank values), so multiplication is needed to get the original full concatenated dimension size. The interleave_fused_lora_weights_for_tp function provides proper validation.

Applied to files:

  • cpp/tensorrt_llm/common/attentionOp.cpp
  • tensorrt_llm/_torch/pyexecutor/model_engine.py
📚 Learning: 2025-08-26T06:07:02.166Z
Learnt from: shaharmor98
Repo: NVIDIA/TensorRT-LLM PR: 7231
File: tensorrt_llm/_torch/pyexecutor/_util.py:504-509
Timestamp: 2025-08-26T06:07:02.166Z
Learning: In tensorrt_llm/_torch/pyexecutor/_util.py, when calling model_engine.set_lora_model_config(), pass model_binding_config.mlp_hidden_size directly without multiplying by mapping.tp_size, as the mlp_hidden_size from get_bindings_model_config() is already the per-TP rank value needed for LoRA weight packaging.

Applied to files:

  • tensorrt_llm/_torch/pyexecutor/model_engine.py
📚 Learning: 2025-08-19T12:45:11.997Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 7033
File: tensorrt_llm/_torch/pyexecutor/model_engine.py:0-0
Timestamp: 2025-08-19T12:45:11.997Z
Learning: In tensorrt_llm/_torch/pyexecutor/model_engine.py, DoRA (Delta Orthogonal Rank Adaptation) functionality was removed from the PyTorch flow to eliminate issues with inverted DoRA detection logic. The original is_dora condition was checking if scaling_vec_pointer == 0, which was potentially incorrect.

Applied to files:

  • tensorrt_llm/_torch/pyexecutor/model_engine.py
📚 Learning: 2025-09-23T15:01:00.070Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/config.cu:15-17
Timestamp: 2025-09-23T15:01:00.070Z
Learning: In TensorRT-LLM NCCL device kernels (cpp/tensorrt_llm/kernels/nccl_device/config.cu), std::ostringstream is used but <sstream> doesn't need to be explicitly included because it's provided transitively through other headers like tensorrt_llm/common/cudaUtils.h or config.h. Local compilation testing confirms this works without the explicit include.

Applied to files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h
📚 Learning: 2025-09-23T15:12:38.312Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/thop/allreduceOp.cpp:352-446
Timestamp: 2025-09-23T15:12:38.312Z
Learning: In TensorRT-LLM NCCL device allreduce implementation (cpp/tensorrt_llm/thop/allreduceOp.cpp), the goto pattern in runNCCLAllReduceDeviceFusion is intentionally used for future extensibility, allowing multiple switch cases to fallback to the default handler. While not aesthetically ideal, this pattern supports adding more fusion cases later that can reuse the same fallback logic.

Applied to files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h
📚 Learning: 2025-08-19T03:35:20.866Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 6915
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:4616-4626
Timestamp: 2025-08-19T03:35:20.866Z
Learning: In the MOE profiler TMA workspace preparation (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu), the overlapping of TMA WS regions for NONE and FINALIZE variants is deliberate design to save memory space, as confirmed by djns99. The comment "reuse the same pointers to save space" reflects this intentional behavior.

Applied to files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu
📚 Learning: 2025-09-23T14:58:05.372Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/config.cu:42-49
Timestamp: 2025-09-23T14:58:05.372Z
Learning: In TensorRT-LLM NCCL device kernels (cpp/tensorrt_llm/kernels/nccl_device/), the token partitioning intentionally uses ceil-like distribution (same token_per_rank for all ranks) to ensure all ranks launch the same number of blocks. This is required for optimal NCCL device API barrier performance, even though it may launch extra blocks for non-existent tokens on later ranks. Runtime bounds checking in the kernel (blockID validation) handles the overshoot cases.

Applied to files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu
📚 Learning: 2025-08-14T06:36:40.701Z
Learnt from: timlee0212
Repo: NVIDIA/TensorRT-LLM PR: 6886
File: tensorrt_llm/_torch/models/modeling_deepseekv3.py:0-0
Timestamp: 2025-08-14T06:36:40.701Z
Learning: In DeepSeek V3 model (tensorrt_llm/_torch/models/modeling_deepseekv3.py), the disagreement between AllReduce.__init__ guard and _compute_mlp_tp_size logic for MNNVL usage is expected by design. The AllReduce component and MLP TP-size computation intentionally use different criteria for MNNVL availability decisions.

Applied to files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h
📚 Learning: 2025-08-08T05:06:31.596Z
Learnt from: sklevtsov-nvidia
Repo: NVIDIA/TensorRT-LLM PR: 3294
File: cpp/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/epilogue/fusion/sm90_visitor_scatter.hpp:36-36
Timestamp: 2025-08-08T05:06:31.596Z
Learning: CUTLASS extension files (under cpp/tensorrt_llm/cutlass_extensions/) follow CUTLASS coding style conventions, including using #pragma once instead of TRTLLM_ prefixed header guards, even though they are .hpp files.

Applied to files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h
📚 Learning: 2025-08-20T07:43:36.447Z
Learnt from: ChristinaZ
Repo: NVIDIA/TensorRT-LLM PR: 7068
File: cpp/tensorrt_llm/kernels/moeTopKFuncs.cuh:169-172
Timestamp: 2025-08-20T07:43:36.447Z
Learning: In TensorRT-LLM MOE kernels, when processing up to 128 experts across 32 threads, each thread handles at most 4 experts (N < 5 constraint), where N represents candidates per thread rather than total system capacity.

Applied to files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h
📚 Learning: 2025-08-18T08:42:02.640Z
Learnt from: samuellees
Repo: NVIDIA/TensorRT-LLM PR: 6974
File: tensorrt_llm/serve/scripts/benchmark_dataset.py:558-566
Timestamp: 2025-08-18T08:42:02.640Z
Learning: In TensorRT-LLM's RandomDataset (tensorrt_llm/serve/scripts/benchmark_dataset.py), when using --random-token-ids option, sequence length accuracy is prioritized over semantic correctness for benchmarking purposes. The encode/decode operations should use skip_special_tokens=True and add_special_tokens=False to ensure exact target token lengths.

Applied to files:

  • cpp/tensorrt_llm/thop/attentionOp.cpp
📚 Learning: 2025-08-08T04:10:19.038Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 6728
File: cpp/tensorrt_llm/plugins/mixtureOfExperts/mixtureOfExpertsPlugin.cpp:966-966
Timestamp: 2025-08-08T04:10:19.038Z
Learning: TensorRT plugins currently don't support padding functionality, and TensorRT is not getting new features (in maintenance mode). This means that duplicating parameters like mExpertHiddenSize in function calls, even with TODO comments, can be acceptable as pragmatic solutions within these constraints.

Applied to files:

  • cpp/tensorrt_llm/thop/attentionOp.cpp
📚 Learning: 2025-09-19T21:28:13.751Z
Learnt from: jhaotingc
Repo: NVIDIA/TensorRT-LLM PR: 7856
File: cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp:159-166
Timestamp: 2025-09-19T21:28:13.751Z
Learning: In TensorRT-LLM blockScaleMoe routing (cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu), the DeepSeek routing method performs reinterpret_cast<float*>(routingLogits) at line 89, which could cause issues if routing_logits are BF16. However, Qwen3-FP8 models use RenormalizeNaive routing method and are not affected by this dtype casting issue.

Applied to files:

  • cpp/tensorrt_llm/thop/attentionOp.cpp
📚 Learning: 2025-07-22T09:22:14.726Z
Learnt from: yechank-nvidia
Repo: NVIDIA/TensorRT-LLM PR: 6254
File: tensorrt_llm/_torch/pyexecutor/model_engine.py:1201-1204
Timestamp: 2025-07-22T09:22:14.726Z
Learning: In TensorRT-LLM's multimodal processing pipeline, shared tensor recovery using `from_shared_tensor()` is only needed during the context phase. Generation requests reuse the already-recovered tensor data and only need to call `strip_for_generation()` to remove unnecessary multimodal data while preserving the recovered tensors. This avoids redundant tensor recovery operations during generation.

Applied to files:

  • cpp/tensorrt_llm/thop/attentionOp.cpp
📚 Learning: 2025-08-22T01:54:35.850Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 7104
File: cpp/tensorrt_llm/kernels/cutlass_kernels/include/moe_kernels.h:999-1000
Timestamp: 2025-08-22T01:54:35.850Z
Learning: The `internal_cutlass_kernels` directory in TensorRT-LLM is a mirror of an internal NVIDIA repository and maintains its own implementation and API that may diverge from the public `cutlass_kernels` version. API inconsistencies between these two directories are intentional and by design, not bugs to be fixed.

Applied to files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu
  • tensorrt_llm/_torch/attention_backend/trtllm.py
📚 Learning: 2025-08-15T06:46:54.897Z
Learnt from: eopXD
Repo: NVIDIA/TensorRT-LLM PR: 6767
File: cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp:0-0
Timestamp: 2025-08-15T06:46:54.897Z
Learning: In cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp addToken function, newly allocated blocks are unshared by design. The beam search path in addToken (when sequence.getNumTokens() > windowSize) is currently broken/non-functional with SWA, so the block allocation doesn't follow a shared-then-unshared pattern.

Applied to files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu
  • cpp/tensorrt_llm/kernels/decoderMaskedMultiheadAttention/xqaParams.h
📚 Learning: 2025-08-21T02:41:10.565Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 7104
File: cpp/tensorrt_llm/kernels/cutlass_kernels/include/moe_gemm_kernels.h:141-145
Timestamp: 2025-08-21T02:41:10.565Z
Learning: In TensorRT-LLM MOE GEMM kernels (cpp/tensorrt_llm/kernels/cutlass_kernels/include/moe_gemm_kernels.h), the stride_act and stride_weight pointers in TmaWarpSpecializedGroupedGemmInput are intentionally declared as void* rather than typed pointers because the actual stride type is determined at runtime based on factors like the swap_ab flag and layout decisions. This runtime type determination makes compile-time type safety impossible, so void* is the correct approach.

Applied to files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaRunnerParams.h
📚 Learning: 2025-08-15T06:46:53.813Z
Learnt from: eopXD
Repo: NVIDIA/TensorRT-LLM PR: 6767
File: cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp:0-0
Timestamp: 2025-08-15T06:46:53.813Z
Learning: In the TensorRT-LLM KV cache manager, SWA (Sliding Window Attention) combined with beam search is currently in a broken/non-functional state and is planned for future rework. During preparatory refactoring phases, code related to SWA+beam search may intentionally remain in a non-working state until the broader rework is completed.

Applied to files:

  • tensorrt_llm/_torch/attention_backend/trtllm.py
  • tests/unittest/_torch/modeling/test_modeling_llama.py
📚 Learning: 2025-08-06T13:58:07.506Z
Learnt from: galagam
Repo: NVIDIA/TensorRT-LLM PR: 6487
File: tests/unittest/_torch/auto_deploy/unit/singlegpu/test_ad_trtllm_bench.py:1-12
Timestamp: 2025-08-06T13:58:07.506Z
Learning: In TensorRT-LLM, test files (files under tests/ directories) do not require NVIDIA copyright headers, unlike production source code files. Test files typically start directly with imports, docstrings, or code.

Applied to files:

  • tensorrt_llm/_torch/attention_backend/trtllm.py
  • tests/unittest/_torch/modeling/test_modeling_llama.py
📚 Learning: 2025-09-09T09:40:45.658Z
Learnt from: fredricz-20070104
Repo: NVIDIA/TensorRT-LLM PR: 7645
File: tests/integration/test_lists/qa/llm_function_core.txt:648-648
Timestamp: 2025-09-09T09:40:45.658Z
Learning: In TensorRT-LLM test lists, it's common and intentional for the same test to appear in multiple test list files when they serve different purposes (e.g., llm_function_core.txt for comprehensive core functionality testing and llm_function_core_sanity.txt for quick sanity checks). This duplication allows tests to be run in different testing contexts.

Applied to files:

  • tensorrt_llm/_torch/attention_backend/trtllm.py
  • tests/unittest/_torch/modeling/test_modeling_llama.py
📚 Learning: 2025-08-21T21:48:35.135Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 7104
File: cpp/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/epilogue/fusion/sm90_visitor_scatter.hpp:399-417
Timestamp: 2025-08-21T21:48:35.135Z
Learning: CUTLASS extensions in TensorRT-LLM (located under cpp/tensorrt_llm/cutlass_extensions/) are designed to integrate with and extend functionality in the external CUTLASS repository. When analyzing these extensions, their consumers and functionality wiring may exist in the CUTLASS codebase rather than within TensorRT-LLM itself.

Applied to files:

  • tensorrt_llm/_torch/attention_backend/trtllm.py
📚 Learning: 2025-08-29T14:07:45.863Z
Learnt from: EmmaQiaoCh
Repo: NVIDIA/TensorRT-LLM PR: 7370
File: tests/unittest/trt/model_api/test_model_quantization.py:24-27
Timestamp: 2025-08-29T14:07:45.863Z
Learning: In TensorRT-LLM's CI infrastructure, pytest skip markers (pytest.mark.skip) are properly honored even when test files have __main__ blocks that call test functions directly. The testing system correctly skips tests without requiring modifications to the __main__ block execution pattern.

Applied to files:

  • tests/unittest/_torch/modeling/test_modeling_llama.py
📚 Learning: 2025-07-28T17:06:08.621Z
Learnt from: moraxu
Repo: NVIDIA/TensorRT-LLM PR: 6303
File: tests/integration/test_lists/qa/examples_test_list.txt:494-494
Timestamp: 2025-07-28T17:06:08.621Z
Learning: In TensorRT-LLM testing, it's common to have both CLI flow tests (test_cli_flow.py) and PyTorch API tests (test_llm_api_pytorch.py) for the same model. These serve different purposes: CLI flow tests validate the traditional command-line workflow, while PyTorch API tests validate the newer LLM API backend. Both are legitimate and should coexist.

Applied to files:

  • tests/unittest/_torch/modeling/test_modeling_llama.py
📚 Learning: 2025-08-26T09:37:10.463Z
Learnt from: jiaganc
Repo: NVIDIA/TensorRT-LLM PR: 7031
File: tensorrt_llm/bench/dataclasses/configuration.py:90-104
Timestamp: 2025-08-26T09:37:10.463Z
Learning: In TensorRT-LLM, the `get_pytorch_perf_config()` method returns `self.pytorch_config` which can contain default `cuda_graph_config` values, so `llm_args` may already have this config before the extra options processing.

Applied to files:

  • tests/unittest/_torch/modeling/test_modeling_llama.py
📚 Learning: 2025-08-26T09:37:10.463Z
Learnt from: jiaganc
Repo: NVIDIA/TensorRT-LLM PR: 7031
File: tensorrt_llm/bench/dataclasses/configuration.py:90-104
Timestamp: 2025-08-26T09:37:10.463Z
Learning: In TensorRT-LLM's bench configuration, the `get_pytorch_perf_config()` method returns `self.pytorch_config` which is a Dict[str, Any] that can contain default values including `cuda_graph_config`, making the fallback `llm_args["cuda_graph_config"]` safe to use.

Applied to files:

  • tests/unittest/_torch/modeling/test_modeling_llama.py
📚 Learning: 2025-08-27T14:23:55.566Z
Learnt from: ixlmar
Repo: NVIDIA/TensorRT-LLM PR: 7294
File: tensorrt_llm/_torch/modules/rms_norm.py:17-17
Timestamp: 2025-08-27T14:23:55.566Z
Learning: The TensorRT-LLM project requires Python 3.10+ as evidenced by the use of TypeAlias from typing module, match/case statements, and union type | syntax throughout the codebase, despite some documentation still mentioning Python 3.8+.

Applied to files:

  • tests/unittest/_torch/modeling/test_modeling_llama.py
🧬 Code graph analysis (9)
cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.h (1)
cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu (2)
  • runPrepareCustomMask (217-241)
  • runPrepareCustomMask (217-218)
cpp/tensorrt_llm/common/attentionOp.cpp (1)
cpp/tensorrt_llm/kernels/decoderMaskedMultiheadAttention/decoderXQAImplPrecompiled.cpp (4)
  • xqaParams (106-135)
  • xqaParams (106-106)
  • xqaParams (137-154)
  • xqaParams (137-137)
cpp/tests/unit_tests/kernels/prepareCustomMaskTest.cpp (2)
cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu (2)
  • runPrepareCustomMask (217-241)
  • runPrepareCustomMask (217-218)
cpp/include/tensorrt_llm/executor/types.h (1)
  • MemoryType (165-646)
cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h (1)
cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu (2)
  • runPrepareCustomMask (217-241)
  • runPrepareCustomMask (217-218)
cpp/tensorrt_llm/thop/attentionOp.cpp (1)
cpp/tests/unit_tests/kernels/prepareCustomMaskTest.cpp (1)
  • isSM100Family (171-174)
cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/prepareCustomMask.cu (1)
cpp/tests/unit_tests/kernels/prepareCustomMaskTest.cpp (4)
  • batchSize (197-361)
  • batchSize (197-198)
  • ceilDiv (46-49)
  • ceilDiv (46-46)
tensorrt_llm/_torch/attention_backend/trtllm.py (2)
tensorrt_llm/_utils.py (1)
  • get_sm_version (733-735)
tensorrt_llm/_torch/attention_backend/interface.py (3)
  • num_seqs (252-256)
  • seq_lens (174-175)
  • seq_lens (178-199)
cpp/tensorrt_llm/common/attentionOp.h (1)
cpp/tensorrt_llm/pybind/batch_manager/kvCacheManager.cpp (2)
  • layer_idx (238-241)
  • layer_idx (238-238)
tests/unittest/_torch/modeling/test_modeling_llama.py (3)
tests/unittest/utils/util.py (1)
  • getSMVersion (61-80)
tensorrt_llm/_torch/attention_backend/trtllm.py (2)
  • prepare (797-884)
  • update_spec_dec_param (1139-1217)
tensorrt_llm/_torch/speculative/utils.py (1)
  • SpecDecodingTensor (253-264)
🪛 Clang (14.0.6)
cpp/tests/unit_tests/kernels/prepareCustomMaskTest.cpp

[error] 18-18: 'gtest/gtest.h' file not found

(clang-diagnostic-error)

⏰ Context from checks skipped due to timeout of 90000ms. You can increase the timeout in your CodeRabbit configuration to a maximum of 15 minutes (900000ms). (1)
  • GitHub Check: Pre-commit Check

@sunnyqgg sunnyqgg force-pushed the qgai/trtllm-gen-tree-attn branch 2 times, most recently from da13f7c to c729898 Compare November 6, 2025 13:45
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sunnyqgg commented Nov 7, 2025

/bot run --disable-fail-fast

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PR_Github #23794 [ run ] triggered by Bot. Commit: b0cb675

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PR_Github #23794 [ run ] completed with state FAILURE. Commit: b0cb675
/LLM/main/L0_MergeRequest_PR pipeline #17911 completed with status: 'FAILURE'

@sunnyqgg sunnyqgg force-pushed the qgai/trtllm-gen-tree-attn branch from b0cb675 to 22d38d7 Compare November 7, 2025 06:20
Signed-off-by: qgai <[email protected]>
@sunnyqgg sunnyqgg force-pushed the qgai/trtllm-gen-tree-attn branch from 22d38d7 to 079d70b Compare November 7, 2025 06:24
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sunnyqgg commented Nov 7, 2025

/bot run --disable-fail-fast

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PR_Github #23819 [ run ] triggered by Bot. Commit: 079d70b

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