This is a tricky one...
Are you saying that RAM size must not include the parity checked one?
Looking at the overview of the Datasheet one might think that there is 128KB of ram.
We may want to check for all families now :D

To be honest, I am not exactly a professional when it comes to working this close to the metal, and I have no idea whether parity checked ram is usually included in the general purpose RAM.

To shortly summarize how I got to think that this change is correct:

• I tried to get the blinky example to work on my STM32L476RG, but couldn't get any output.
• Upon searching for the error, I stumbled upon Run time error on L476 due to wrong RAM size. #71 and the supposed size of 96K for the RAM
• I followed a tutorial from STM for the STM32CubeIDE to get the LED to blink and compared whats different. The generated file STM32L476RGTX_RAM.ld, which seem to have the same purposes as the L476RG.ld generated by stm32-cmake, specifies a RAM size of 96K. See the excerpt below.
• Debugging the binary generated by the CubeIDE with gdb and inspecting _estack really gives a value of 0x20018000, which equals the the stackoffset of 0x20000000 + 96K. Inspecting the same value in the binary generated with stm32-cmake gives 0x20020000. In this case, the application seems to hang in startup_stm32l476xx.s on the line ldr sp, =_estack, even though I am not sure if this is just a quirk of gdb.
• Finally, changing the RAM size to 96K fixes my problem and the LED blinked happily ever after

/* Highest address of the user mode stack */
_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */

_Min_Heap_Size = 0x200;	/* required amount of heap  */
_Min_Stack_Size = 0x400;	/* required amount of stack */

/* Memories definition */
MEMORY
{
  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 96K
  RAM2    (xrw)    : ORIGIN = 0x10000000,   LENGTH = 32K
  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 1024K
}
//...

@Hish15 I had a look at datasheet. this part has 128kB of SRAM in total the problem is that they are separated in 2 banks
From datasheet section 3.15:

• 96 Kbyte mapped at address 0x2000 0000 (SRAM1)
• 32 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).

So 96k is correct but there should be a way to declare the other section too.

Edit: please see my review comment

Thanks @atsju
In this PR is ok to handle SRAM1 when SRAM2 is not right after it.
Another PR might handle SRAM2 in this particular case (or not 😄)
What do you think?

As @Hish15 seems to be ok with the changes from @atsju, I've included them in this PR 🙂

Hi @Staff-d
I just wanted to inform you that I included the changes you proposed into #165.
It goes a bit further as I checked all supported series to apply the same modifications.

Hi @Staff-d
I just wanted to inform you that I included the changes you proposed into #165.
It goes a bit further as I checked all supported series to apply the same modifications.

@atsju In this case, I'll close this PR and hope yours gets merged soon 🙂