Thanks to visit codestin.com
Credit goes to github.com

Skip to content

fix "longint" & "unique case" bugs #24

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 2 commits into
base: master
Choose a base branch
from
Open

fix "longint" & "unique case" bugs #24

Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
f4208e0
fix "longint" & "unique" bugs
zhutmost Feb 9, 2017
0333053
fix "unique case" & "longint" bugs
zhutmost Feb 9, 2017
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 2 additions & 6 deletions grammars/verilog.cson
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -57,10 +57,6 @@
'match': '\\b[0-9]+\'[bBoOdDhH][a-fA-F0-9_xXzZ]+\\b'
'name': 'constant.numeric.sized_integer.verilog'
}
{
'match': '\\s\'[bBoOdDhH][a-fA-F0-9_xXzZ]+\\b'
'name': 'constant.numeric.unsized_integer.verilog'
}
{
'captures':
'1':
Expand Down Expand Up @@ -95,7 +91,7 @@
'include': '#keywords'
}
{
'begin': '^\\s*([a-zA-Z][a-zA-Z0-9_]*)\\s+([a-zA-Z][a-zA-Z0-9_]*)(?<!begin|if)\\s*(?=\\(|$)'
'begin': '^\\s*([a-zA-Z][a-zA-Z0-9_]*)\\s+([a-zA-Z][a-zA-Z0-9_]*)(?<!begin|if|case)\\s*(?=\\(|$)'
'beginCaptures':
'1':
'name': 'entity.name.tag.module.reference.verilog'
Expand Down Expand Up @@ -142,7 +138,7 @@
'keywords':
'patterns': [
{
'match': '\\b(alias|always|always_comb|always_ff|always_latch|and|assert|assign|assume|attribute|automatic|begin|before|bind|bins|binsof|bit|break|buf|bufif0|bufif1|byte|case(xz)?|cell|chandle|class|clocking|cmos|config|const|constraint|context|continue|cover|covergroup|coverpoint|cross|dist|do|deassign|default|defparam|design|disable|edge|else|end(attribute|case|class|clocking|config|function|generate|group|interface|module|package|primitive|program|property|sequence|specify|table|task)?|enum|event|expect|export|extends|extern|final|first_match|for|foreach|force|forever|fork|forkjoin|function|generate|genvar|incdir|include|instance|highz(01)|if(none|f)?|ignore_bins|import|initial|inout|input|inside|integer|int|interface|interact|join|join_any|join_none|large|liblist|library|local|logic|localparam|longing|matches|medium|module|modport|macromodule|nand|negedge|new|nmos|nor|noshowcancelled|not|notif(01)|null|or|output|package|packed|parameter|pmos|posedge|primitive|priority|program|property|protected|pull0|pull1|pulldown|pullup|pulsestyle_onevent|pulsestyle_ondetect|pure|rand|randc|randcase|randsequence|rcmos|real|realtime|ref|reg|release|repeat|return|rnmos|rpmos|rtran|rtranif(01)|scalared|sequence|semaphore|shortint|shortreal|showcancelled|signed|small|solve|specify|specparam|static|strength|string|strong0|strong1|struct|super|supply0|supply1|table|tagged|task|this|throughout|time|timeprecision|timeunit|type|typedef|ran|tranif(01)|tri(01)?|tri(and|or|reg)|union|unique|unsigned|use|uwire|var|vectored|virtual|void|wait|wait_order|wand|weak(01)|wildcard|while|with|within|wire|wor|xnor|xor)\\b'
'match': '\\b(alias|always|always_comb|always_ff|always_latch|and|assert|assign|assume|attribute|automatic|begin|before|bind|bins|binsof|bit|break|buf|bufif0|bufif1|byte|case(xz)?|cell|chandle|class|clocking|cmos|config|const|constraint|context|continue|cover|covergroup|coverpoint|cross|dist|do|deassign|default|defparam|design|disable|edge|else|end(attribute|case|class|clocking|config|function|generate|group|interface|module|package|primitive|program|property|sequence|specify|table|task)?|enum|event|expect|export|extends|extern|final|first_match|for|foreach|force|forever|fork|forkjoin|function|generate|genvar|incdir|include|instance|highz(01)|if(none|f)?|ignore_bins|import|initial|inout|input|inside|integer|int|interface|interact|join|join_any|join_none|large|liblist|library|local|logic|localparam|longint|matches|medium|module|modport|macromodule|nand|negedge|new|nmos|nor|noshowcancelled|not|notif(01)|null|or|output|package|packed|parameter|pmos|posedge|primitive|priority|program|property|protected|pull0|pull1|pulldown|pullup|pulsestyle_onevent|pulsestyle_ondetect|pure|rand|randc|randcase|randsequence|rcmos|real|realtime|ref|reg|release|repeat|return|rnmos|rpmos|rtran|rtranif(01)|scalared|sequence|shortint|shortreal|showcancelled|signed|small|solve|specify|specparam|static|strength|string|strong0|strong1|struct|super|supply0|supply1|table|tagged|task|this|throughout|time|timeprecision|timeunit|type|typedef|ran|tranif(01)|tri(01)?|tri(and|or|reg)|union|unique|unsigned|use|uwire|var|vectored|virtual|void|wait|wait_order|wand|weak(01)|wildcard|while|with|within|wire|wor|xnor|xor)\\b'
'name': 'keyword.other.verilog'
}
{
Expand Down