soc

Used to record my SoC design experience

Tools

https://www.veripool.org/
https://www.edaplayground.com/
https://www.shiyanlou.com/

http://www.asic-world.com/
http://www.asic-world.com/verilog/tools.html

IPs

• OpenCore
• Open Hardware for Chip Designers
  https://github.com/parallella/oh

SoCs

• ARM designstart
  • A demo SoC
  • system testbench example
  • simulation environment
    • compile the test code
    • compile the RTL
    • run the simulation
  • Software Examples
    • driver files
    • retargeting
  • Implementation
    • constraints
    • synthesis
    • dft
• Risc-v
  *