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anirudhrb · 2026-03-25T08:58:30Z

This pull request refactors and enhances the handling of CPU cache topology information for aarch64. It moves cache information utilities into a dedicated module, updates the ACPI PPTT (Processor Properties Topology Table) construction to include detailed cache hierarchy data, and adds an integration test to verify that cache topology is correctly exposed to guests. Additionally, it updates dependencies and improves code organization.

Aarch64 cache topology refactor and enhancements:

Moved cache information functions and the CacheLevel enum from fdt.rs to a new arch/src/aarch64/cache.rs module, and updated imports accordingly for better code organization and reuse.
Refactored the aarch64 ACPI PPTT table construction in CpuManager::create_pptt to use the new cache module, and now populates the PPTT with detailed cache hierarchy (L1d, L1i, L2, L3) information as available from sysfs, using the acpi_tables crate's PPTT API.

Testing and validation:

Added an integration test (test_cache_topology) to verify that the guest sees the same cache sizes as the host, ensuring the PPTT and cache information are correctly exposed.

Other improvements:

Updated ACPI table generation to use the helpers from the acpi_tables crate.

rbradford · 2026-03-25T10:37:30Z

Hi @anirudhrb acpi_tables 0.2.1 is now published for you to consume!

anirudhrb · 2026-03-25T10:43:28Z

Hi @anirudhrb acpi_tables 0.2.1 is now published for you to consume!

Awesome! Thanks @rbradford!

phip1611 · 2026-04-09T10:33:56Z

please fix the CI so we can move this forward

rbradford · 2026-04-14T22:31:41Z

@anirudhrb What's blocking on this PR - it's still marked as draft

anirudhrb · 2026-04-15T12:53:26Z

@anirudhrb What's blocking on this PR - it's still marked as draft

It was the CI but I've fixed that now.

rbradford · 2026-04-16T17:01:16Z


                for core_idx in 0..cores_per_package {
-                    let core_offset = pptt.len() - pptt_start;
+                    // let core_offset = pptt.len() - pptt_start;


Commented out code.

rbradford · 2026-04-16T17:02:42Z

@@ -0,0 +1,125 @@
+// Copyright 2020 Arm Limited (or its affiliates). All rights reserved.


Is this copyright header accurate?

Yeah it's copied from fdt.rs since the code is moved from there.

rbradford · 2026-04-16T17:04:34Z

+        src_digits
+            * match src_unit {
+                "K" => 1024,
+                "M" => 1024u32.pow(2),


1 << 20 and 1 << 30

rbradford · 2026-04-16T17:04:53Z

+                "K" => 1024,
+                "M" => 1024u32.pow(2),
+                "G" => 1024u32.pow(3),
+                _ => 1,


Risky but I guess OK

rbradford · 2026-04-16T17:06:03Z

+
+    let file_path = Path::new(&file_directory);
+    if file_path.exists() {
+        let src = fs::read_to_string(file_directory).expect("File not exists or file corrupted.");


Not allowed to panic for "possible" runtime issues (only for programming or really unexpected issues)- need to raise an error.

Oh. I see this was in the existing code! Bad - you don't need to fix but if you do - do as a separate commit. Otherwise create an issue.

Yup, all the code in arch/src/aarch64/cache.rs is existing code just extracted to a new file. I'll fix it anyway.

Created #8097 for this. We'll need to change multiple places outside this file in order to propagate an Error.

rbradford · 2026-04-19T18:05:15Z

Since you've got some changes planned i'll draft this. When you've made your changes please undraft and we can take another look!

rbradford · 2026-04-25T12:30:12Z

This struct is now unused - please delete it

rbradford · 2026-04-25T12:31:44Z

-                    num_private_resources: 0,
-                };
-                pptt.append(cluster_hierarchy_node);
+                use acpi_tables::pptt::ProcessorNode;


Use should be at the top of the file or the top of the test mod if test only.

rbradford · 2026-04-29T13:18:25Z

I think some reordering of the commits might improve the bisectability/churn:

What about:
a. 2c14fac — switch PPTT to acpi_tables helpers
b. 887250b — move cache helpers to cache.rs
c. 3e26d6763 — bit-shift cleanup (small, fits naturally next to the move)
d. New commit: extract CacheTopologyInfo + read_cache_topology() and migrate fdt.rs to it (current e653ebac8
minus the cpu.rs chunk)
e. 276f31242 — add PPTT cache info, but written from the start against read_cache_topology() (no
duplication ever introduced)
f. 0d865be7b — integration test

rbradford

Otherwise lgtm.

anirudhrb · 2026-04-30T09:53:52Z

I think some reordering of the commits might improve the bisectability/churn:

What about: a. 2c14fac — switch PPTT to acpi_tables helpers b. 887250b — move cache helpers to cache.rs c. 3e26d67 — bit-shift cleanup (small, fits naturally next to the move) d. New commit: extract CacheTopologyInfo + read_cache_topology() and migrate fdt.rs to it (current e653eba minus the cpu.rs chunk) e. 276f312 — add PPTT cache info, but written from the start against read_cache_topology() (no duplication ever introduced) f. 0d865be — integration test

Done!

rbradford

Really close - just dubious warn!

rbradford · 2026-05-01T13:56:17Z

+        // Add cache info.
+        let cache_info = read_cache_topology();
+        if cache_info.is_none() {
+            warn!("cache sysfs system does not exist.");


Nit this warning does not look like anything else in the repo (capitalizatiom, etc. Shouldn't this just error out instead?

This warning is the same as the one in fdt.rs. I don't think we should error out - we can continue without the cache topology info.

Okay the style just needs to match the rest of the repo (this may not have been something you introduced but the review made it visible.)

rbradford · 2026-05-18T11:28:26Z

@anirudhrb Ping? Any progress update on this?

anirudhrb · 2026-05-19T09:10:36Z

@anirudhrb Ping? Any progress update on this?

I was able to get my hands on the image. Looking into the issue. I'll un-draft when ready.

rbradford · 2026-06-08T12:32:22Z

@anirudhrb Any update on this?

anirudhrb · 2026-06-09T17:59:57Z

@rbradford I still don't have an environment where I can reproduce this issue. The one KVM box I have is somehow not able to boot the Windows images we use here. I'll try with another one.

anirudhrb · 2026-06-11T09:13:13Z

@rbradford some progress finally! I now have a repro environment and I ran some experiments using copilot. Turns out Windows breaks when I use PPTT revision 3 with 28 byte cache nodes. Changing it to revision 2 (with 24 byte cache nodes - no cache ID) makes Windows happy. I suspect we have slightly old build in our CI which doesn't support PPTT revision 3.

I'm planning to modify the acpi_tables crate to support rev 2 as well and then update this PR to use rev 2.

rbradford · 2026-06-12T11:20:00Z

@rbradford some progress finally! I now have a repro environment and I ran some experiments using copilot. Turns out Windows breaks when I use PPTT revision 3 with 28 byte cache nodes. Changing it to revision 2 (with 24 byte cache nodes - no cache ID) makes Windows happy. I suspect we have slightly old build in our CI which doesn't support PPTT revision 3.

I'm planning to modify the acpi_tables crate to support rev 2 as well and then update this PR to use rev 2.

Or we could have a newer Windows image? (I would like a named individual or team to own Windows guest support for CH). I'm happy to just disable that test for ARM64 windows support in the interim.

anirudhrb · 2026-06-16T10:14:05Z

@rbradford some progress finally! I now have a repro environment and I ran some experiments using copilot. Turns out Windows breaks when I use PPTT revision 3 with 28 byte cache nodes. Changing it to revision 2 (with 24 byte cache nodes - no cache ID) makes Windows happy. I suspect we have slightly old build in our CI which doesn't support PPTT revision 3.
I'm planning to modify the acpi_tables crate to support rev 2 as well and then update this PR to use rev 2.

Or we could have a newer Windows image? (I would like a named individual or team to own Windows guest support for CH). I'm happy to just disable that test for ARM64 windows support in the interim.

Yeah that's one way forward.

@weltling what do you think of this? Is it possible to update the Windows image anytime soon?

@rbradford are you against the approach of presenting revision 2 PPTT nodes from Cloud Hypervisor?

rbradford · 2026-06-16T10:57:24Z

@rbradford some progress finally! I now have a repro environment and I ran some experiments using copilot. Turns out Windows breaks when I use PPTT revision 3 with 28 byte cache nodes. Changing it to revision 2 (with 24 byte cache nodes - no cache ID) makes Windows happy. I suspect we have slightly old build in our CI which doesn't support PPTT revision 3.
I'm planning to modify the acpi_tables crate to support rev 2 as well and then update this PR to use rev 2.

Or we could have a newer Windows image? (I would like a named individual or team to own Windows guest support for CH). I'm happy to just disable that test for ARM64 windows support in the interim.

Yeah that's one way forward.

@weltling what do you think of this? Is it possible to update the Windows image anytime soon?

@rbradford are you against the approach of presenting revision 2 PPTT nodes from Cloud Hypervisor?

No, i'm not against that - I was just offering you alternative options to help you move forward. This PR has been open a long time with not much progress recently. It was obviously an important feature to you since you took the time to open it and implement it.

weltling · 2026-06-16T12:09:53Z

@rbradford some progress finally! I now have a repro environment and I ran some experiments using copilot. Turns out Windows breaks when I use PPTT revision 3 with 28 byte cache nodes. Changing it to revision 2 (with 24 byte cache nodes - no cache ID) makes Windows happy. I suspect we have slightly old build in our CI which doesn't support PPTT revision 3.
I'm planning to modify the acpi_tables crate to support rev 2 as well and then update this PR to use rev 2.

Or we could have a newer Windows image? (I would like a named individual or team to own Windows guest support for CH). I'm happy to just disable that test for ARM64 windows support in the interim.

Yeah that's one way forward.
@weltling what do you think of this? Is it possible to update the Windows image anytime soon?
@rbradford are you against the approach of presenting revision 2 PPTT nodes from Cloud Hypervisor?

No, i'm not against that - I was just offering you alternative options to help you move forward. This PR has been open a long time with not much progress recently. It was obviously an important feature to you since you took the time to open it and implement it.

@anirudhrb @rbradford Unfortunately I lost the Windows guest image for aarch64 topic from the radar. I will plan to come up with a new image till the end of this month, if it's acceptable.

Thanks

anirudhrb · 2026-06-18T07:33:39Z

@rbradford if we want to temporarily disable tests, we'll have to disable all Windows tests on arm64. Because Windows doesn't boot at all with these changes.

rbradford · 2026-07-06T11:11:21Z

I've rebased as @weltling has updated the windows ARM image.

Use the helpers from the acpi_tables crate to construct the PPTT. This is in preparation for adding cache hierarchy info to the PPTT which is simpler using the helpers. Signed-off-by: Anirudh Rayabharam <[email protected]>

fdt.rs has helper functions to query host cache details (topology, size etc.). Extract these helpers to a new file cache.rs so that they can be used for PPTT construction as well. No functional change. Signed-off-by: Anirudh Rayabharam <[email protected]>

Replace 1024, 1024u32.pow(2), and 1024u32.pow(3) with 1u32 << 10, 1u32 << 20, and 1u32 << 30 in get_cache_size. The shift form makes the binary (KiB/MiB/GiB) nature of the conversion immediately obvious and is easier to read at a glance. Signed-off-by: Anirudh Rayabharam <[email protected]>

Both arch/src/aarch64/fdt.rs and vmm/src/cpu.rs declared the same ~14 cache info locals (size/line_size/sets for L1D/L1I/L2/L3, plus shared flags for L2/L3), checked for /sys/devices/system/cpu/cpu0/cache, and populated those locals via get_cache_size / get_cache_coherency_line_size / get_cache_number_of_sets / get_cache_shared. Two near-identical ~30-line blocks. Add a CacheTopologyInfo struct in arch/src/aarch64/cache.rs whose field names mirror the existing locals, plus a read_cache_topology() helper that returns None when the sysfs hierarchy is missing and only queries get_cache_shared for L2/L3 when their size is non-zero (preserving current behavior). Both call sites now obtain the info via read_cache_topology() and destructure it back into locals of the same name, so all downstream references are unchanged. Assisted-by: Copilot-CLI:Claude-Opus-4.7 Signed-off-by: Anirudh Rayabharam <[email protected]>

Read the host cache info from sysfs and pass through the same to the guest via the PPTT table. This is the same as the approach taken for FDT. Similar to that, assume that the L3 cache is always shared and the L2 cache is unique per CPU. Signed-off-by: Anirudh Rayabharam <[email protected]>

Add an integration test to verify the newly added code to expose cache topology information in PPTT. Signed-off-by: Anirudh Rayabharam <[email protected]>

anirudhrb requested a review from a team as a code owner March 25, 2026 08:58

anirudhrb force-pushed the acpi_pptt_new branch 2 times, most recently from 21754e3 to 28bd959 Compare March 25, 2026 10:04

anirudhrb force-pushed the acpi_pptt_new branch from 28bd959 to 933b032 Compare March 26, 2026 11:19

anirudhrb force-pushed the acpi_pptt_new branch from 933b032 to 77cf815 Compare April 7, 2026 13:44

likebreath marked this pull request as draft April 10, 2026 01:19

anirudhrb force-pushed the acpi_pptt_new branch 2 times, most recently from 895189b to ef15bf9 Compare April 12, 2026 04:45

anirudhrb force-pushed the acpi_pptt_new branch from ef15bf9 to 34157d9 Compare April 15, 2026 12:52

anirudhrb marked this pull request as ready for review April 15, 2026 12:52

rbradford requested changes Apr 16, 2026

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rbradford marked this pull request as draft April 19, 2026 18:05

anirudhrb force-pushed the acpi_pptt_new branch from 596740b to 36d37eb Compare April 25, 2026 02:45

anirudhrb mentioned this pull request Apr 25, 2026

Raise Error instead of panic for runtime issues in cache utilities #8097

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anirudhrb marked this pull request as ready for review April 25, 2026 03:02

rbradford requested changes Apr 25, 2026

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anirudhrb force-pushed the acpi_pptt_new branch 2 times, most recently from 5b76aaa to e653eba Compare April 28, 2026 14:56

rbradford reviewed Apr 29, 2026

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anirudhrb force-pushed the acpi_pptt_new branch from e653eba to f1d642f Compare April 30, 2026 09:35

rbradford requested changes May 1, 2026

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anirudhrb force-pushed the acpi_pptt_new branch 2 times, most recently from bb8d17c to 063da72 Compare June 10, 2026 12:32

rbradford force-pushed the acpi_pptt_new branch from 063da72 to 3f14649 Compare July 6, 2026 11:10

anirudhrb added 6 commits July 6, 2026 12:29

vmm: use acpi_tables helpers for PPTT

de2cbac

Use the helpers from the acpi_tables crate to construct the PPTT. This is in preparation for adding cache hierarchy info to the PPTT which is simpler using the helpers. Signed-off-by: Anirudh Rayabharam <[email protected]>

tests: add integration test for PPTT cache topology

ba98d15

Add an integration test to verify the newly added code to expose cache topology information in PPTT. Signed-off-by: Anirudh Rayabharam <[email protected]>

rbradford force-pushed the acpi_pptt_new branch from 3f14649 to ba98d15 Compare July 6, 2026 11:30

rbradford marked this pull request as ready for review July 6, 2026 16:31

rbradford added this pull request to the merge queue Jul 6, 2026

Merged via the queue into cloud-hypervisor:main with commit 0b150ea Jul 6, 2026
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rbradford added this to Cloud Hypervisor Roadmap Jul 8, 2026

github-project-automation Bot moved this to 🆕 New in Cloud Hypervisor Roadmap Jul 8, 2026

github-project-automation Bot moved this from 🆕 New to ✅ Done in Cloud Hypervisor Roadmap Jul 8, 2026

rbradford added the bug-fix Bug fix to include in release notes label Jul 10, 2026

rhakobyan mentioned this pull request Sep 2, 2026

aarch64: Support running integration tests on Graviton4 #8830

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		@@ -0,0 +1,125 @@
		// Copyright 2020 Arm Limited (or its affiliates). All rights reserved.

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