pci: Handle dword MSI-X control writes - #7956
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Some guests update the MSI-X capability through a 32-bit write at offset 0 instead of a 16-bit write at offset 2. Update the cached Message Control state for that path as well so MSI-X enablement stays in sync with the guest configuration. Add a short comment documenting why the dword write path also updates the cached MSI-X Message Control state. This is important for passthrough GPUs, where MSI-X interrupts are used during NVIDIA Fabric Manager registration. Without updating the cached state on the dword write path, interrupt delivery can remain stale and GPU initialization or fabric registration can fail. Signed-off-by: Damian Barabonkov <[email protected]>
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DamianB-BitFlipper
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Summary
0instead of only a 16-bit write at offset2.