PTAL @kunalspathak @TIHan @VSadov @dotnet/jit-contrib

Mostly text diffs since the codegen size is the same. A couple of regressions because ldr + dmb can encode addressing modes, but when we switch to ldapr - we no longer can contain it, we can do it only with armv8.4 LDAPUR, but our SPMI collections don't have this ISA

ping @kunalspathak @TIHan

Not sure if I understand this...in the asmdiff above, we are loading/storing int value instead of float value?

-           ldr     d0, [x0]
-           dmb     ishld
+           ldar    x0, [x0]
+           fmov    d0, x0

@kunalspathak

Not sure if I understand this...in the asmdiff above, we are loading/storing int value instead of float value?

-           ldr     d0, [x0]
-           dmb     ishld
+           ldar    x0, [x0]
+           fmov    d0, x0

So

-           ldr     d0, [x0]
-           dmb     ishld

means "let's load a 4-byte float from x0 memory directly into simd(float) reg". Since there is no acq-release kind of ldr (you can't do ldar d0, [x0]) for SIMD destination, we have to emit an explicit memory barrier.

So in order to workaround it, we do this 4-byte load into a GPR reg (int) first, so we can avoid emitting a memory barrier since ldar gives us the needed semantics already, and then we just move it to a float reg, hence, fmov d0, x0

Effectively, we do:

float foo;

float LoadVolatile()
{
    return Unsafe.BitCast<int, float>
        (Volatile.Read(
            ref Unsafe.As<float, int>(ref foo)));
}

Native compiles use the same trick, e.g.: https://godbolt.org/z/KKTh79xbc

Improvements:

• [Perf] Linux/arm64: 22 Improvements on 5/3/2024 2:25:46 AM perf-autofiling-issues#34053